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HIP7020AB PDF даташит

Спецификация HIP7020AB изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «J1850 Bus Transceiver For Multiplex Wiring Systems».

Детали детали

Номер произв HIP7020AB
Описание J1850 Bus Transceiver For Multiplex Wiring Systems
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HIP7020AB Даташит, Описание, Даташиты
HIP7020
June 1998
J1850 Bus Transceiver
For Multiplex Wiring Systems
Features
Description
• J1850 Bus Transceiver for MX Wiring
• 5V CMOS/TTL Logic Interface
• Current Controlled Transmitter Driver
• Controlled Rise/Fall Time of Bus Drive for Both
Voltage and Current
• Bus Drive Capability to Less Than 500with a 5µs
Load RC Time Constant
• Filtered Bus Input Receiver
• Ground Fault Tolerant for Bus Isolation
• Short Circuit and Over Temperature Protection
• Protection for Reverse Battery, Load Dump
and Latch-Up
±9kV ESD Protection BUS OUT and BATTERY Pins
• -40oC to 125oC Operating Range
• Loop-Back Fault Detection Mode
• 4x (41.6kHz) Receive Speed
Ordering Information
PART
NUMBER
HIP7020AB
HIP7020AP
TEMP.
RANGE (oC)
PACKAGE PKG. NO.
-40 to 125 8 Ld SOIC
M8.15
-40 to 125 8 Ld PDIP
E8.3
The HIP7020 IC is an Integrated I/O Bus Transceiver
designed for the SAE Standard J1850 Class B Data Com-
munication Network Interface. The Bus transmits and
receives data on a single wire using a 10.4kHz VPWM (Vari-
able Pulse Width Modulated) signal. The HIP7020 serves as
an I/O buffer interfacing to 5V CMOS logic. It is designed to
operate directly from the 12V battery line of an automobile.
The normal Bus voltage swing capability is from 0V to 7.75V
at currents greater than 20mA.
As shown in the Block Diagram, the Transmitter TX Input and
the Receiver RX Output of the Bus Transceiver Circuit inter-
face to the control logic. The TX input signal is wave shaped
for rise time, fall time and amplitude before it is converted
from voltage to current. The Wave Shaper with an external
programming resistor, RS controls the rise and fall time of
the BUS OUT output signal. The current source drive to the
Bus is voltage controlled by the Wave Shaped Voltage Refer-
ence to a maximum limit as specified for the J1850 Bus and
includes short-circuit current limiting.
The HIP7020 Receiver input, BUS IN is connected to the
J1850 Bus through an external resistor, RF and has a trip
point at one-half of the nominal Bus signal voltage which is
3.875V. The Receiver input is filtered to remove high fre-
quency Bus noise by the external resistor and an internal
capacitor. The Receiver Bus signal, after processing, is out-
put at the RX pin by the RX Buffer’s open collector driver.
The RX output is active low and requires an external pull-up
resistor returned to the control logic VCC supply. This pre-
vents power-up of the control logic by the transceiver if VCC
supply voltage is removed.
The HIP7020 has a Loop-Back Enable Mode Switch to
return diagnostic information for the Bus Transceiver node.
For an active low or an open LB EN input, the Trans-
mit/Receive signals are internally “Looped-Back” to provide
a TX to RX return signal path independent of signals on the
Bus. A return path validation indicates proper action of the
Bus Transceiver apart from the J1850 Bus.
Pinout
HIP7020
(PDIP, SOIC)
TOP VIEW
BATT 1
TX 2
R/F TIME 3
RX 4
8 GND
7 BUS OUT
6 LB EN
5 BUS IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3642.3









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HIP7020AB Даташит, Описание, Даташиты
Block Diagram
TX
R/F
TIME
R/F TIME
RS
GND
LB EN
VCC
RD
RX
HIP7020
TX
BUF
ISTX
WAVE
SHAPER
WAVE
SHAPED
VOLT. REF
VREF
VOLTAGE TO
CURRENT
CONVERTER
OVER-
TEMP SW
BATT
V+
DIAGNOSTIC
LOOP-BACK
MODE SW
ISLB SWITCH SHOWN IN
LOOP-BACK MODE
RX
BUF
BUS RCVR AND
VOLT. COMP.
LEVEL
SHIFTER
Q1 VBO
BUS OUT
RE
RF
IBO
FILTER
BUS IN
HIP7020
Applications
The circuit of Figure 1 illustrates the essential elements of
the J1850 Bus Transceiver in a normal application. For nor-
mal J1850 applications, a Bus Transceiver is used at each
system node. The Electrical Specifications Table also refers
to the peripheral components shown in Figure 1 and the
Block Diagram for the HIP7020 Bus Transceiver.
HIP7030A2
CONTROLLER
HOST
µC
HOST
µC
HIP7010
BYTE LEVEL
INTERFACE
CIRCUIT
HIP7020
BUS
TRANSCEIVER
HIP7030A2
µC
HIP7020
BUS
TRANSCEIVER
MOV
M1
(NOTE)
LB EN TX RX
BUS OUT
BATT
C1
0.01µF
J1850 BUS
TRANSCEIVER
RE
10
RF
15K
BUS IN
R/F GND
RS 56.2K
J1850 BUS
RBS
CBS RBS = 500TO 1500
τ = RBSCBS 5µs
NOTE: MOV, M1 represents central protection, normally on the
alternator and with a typical value in the range of 27V to 40V.
FIGURE 1. TYPICAL APPLICATION CIRCUIT DIAGRAM
HIP7030A2
µC
HIP7020
BUS
TRANSCEIVER
FIGURE 2. TYPICAL J1850 SYSTEM CONFIGURATIONS
NOTE: The R/F bias resistor, RS, should be located as close as
possible to the IC to minimize noise coupling to the R/F
pin. The ground connection of RS must be made directly
to the GND pin of the IC with no other current flowing in
the connecting line to prevent system ground currents
from affecting the rise/fall time control of the Wave
Shaper. The RS resistor value is typically specified as 1%
tolerance. If an R/F bypass capacitor is used to filter
noise, the value should be 100pF or less. For effective
noise filtering, the R/F bypass capacitor should be con-
nected direct from the R/F pin to the GND pin and should
not carry current from other sources.
Figure 2 illustrates some of the typical J1850 System
Configurations that utilize the HIP7020 Bus Transceiver.
Refer to the HIP7010 and HIP7030A2 Data Sheets for
further information on J1850 System Configuration detail.
2









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HIP7020AB Даташит, Описание, Даташиты
HIP7020
Absolute Maximum Ratings
Supply Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . -20V to +24V
Short Term Supply Voltage, VBATT, 1s Max. (Note 2) . . . . . . . +35V
J1850 Bus Input Voltage, VBUS IN . . . . . . . . . . . . . . . . . . . . . . ±20V
J1850 Bus Load Current, IBO. . . . . . . . . . . . . . . . . . . . .Self-Limiting
TX Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
RX Logic Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Load Dump (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
BUS Transient Susceptibility . . . . . . . . . . . . . . . . . . . . . . . (Note 3)
ESD: BUS OUT, BATTERY Pins, (Air Gap, Note 4) . . . . . . ±9kV
BUS OUT, BATTERY Pins, (Direct, Note 4) . . . . . ±4.5kV
All Other Pins (Direct, Note 4) . . . . . . . . . . . . . . . . . . ±2kV
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-40oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Fault capability of the J1850 Bus Transceiver includes reverse battery, load dump and latch-up tolerance to ±200mA on any terminal. The
Short Term Power Supply Voltage capability is 35V for a maximum of 1s. Continued operation at this voltage may cause thermal shutdown.
3. Transient Susceptibility Bus and Battery Pins Per SAE J1113, Aug 1987, Figures 7 Test Pulses 1, 2, 3A and 3B at -50V, +100V and ±200V
respectively.
4. ESD Conditions - SAE J1113; Aug 1987. BUS OUT & BATTERY Pins: Air Gap and Direct Contact Discharge; R = 2k, C = 150pF
All Other Pins: Direct Contact Discharge; R = 1.5k, C = 100pF
Electrical Specifications
9.0V VBATT 16V; RS = 56.2kΩ ±1%; except as noted, RBS = 500to 1500and τ = RBSCBS = 5µs.
All voltages are measured with respect to ground and the TA Range of -40oC to 125oC shall not be
exceeded during test unless otherwise specified. For test detail, refer to the Block Diagram, Figures 3
and 4 Test Circuits and Figures 5 and 6 Waveforms.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Idle Supply Current
Operating Voltage Range
Supply Current,
BUS OUT Short to GND
IBATT
VBATT
IBATT(SG)
BUS OUT Open; No Bus Signal;
VBATT = 12.6V; VTX Low
(Note 5)
BUS OUT Short to GND, VTX High
90 200 350
µA
6 - 24 V
20 - 50 mA
Supply Current,
BUS OUT Short to BATT
IBATT(SB) BUS OUT to VBATT; IBO = 0 mA
Thermal Shutdown Temperature
TSD
Thermal Shutdown Hysteresis
TSDHYS
TX CMOS/TTL INPUT WITH/PULL DOWN
(Note 6)
(Note 6)
VTX High 2 - 8 mA
VTX Low 90
- 350 µA
150 - 170 oC
5 10 15 oC
Input Bias Current, TX
Input Low Voltage
Input High Voltage
Input Capacitance
BUS OUT
ITX
VIL
VIH
CTX
VTX = 7V; (Note 7)
20 - 38 µA
-
- 0.8
V
2.0 -
-
V
2 - 5 pF
BUS OUT High Voltage
BUS OUT Low Voltage
BUS OUT Voltage, Low Battery
VBOH VTX High
VBOL Bus Load, RBS = 1.5k; VTX Low
VBOH(PSL) 6V VBATT < 9V; VTX High
6.6
-
Note
13
-
-
-
8.5
0.1
8.5
V
V
V
Source Current, Bus Low
BUS OUT During LOOPBACK
IBO_LIMIT -20V VBUS OUT < [VBOH (Measured) - 0.8V];
VTX High
VLOOPBACK LB EN Low, VTX High
-20 - -42 mA
- -1 V
3










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Номер в каталогеОписаниеПроизводители
HIP7020ABJ1850 Bus Transceiver For Multiplex Wiring SystemsIntersil Corporation
Intersil Corporation
HIP7020APJ1850 Bus Transceiver For Multiplex Wiring SystemsIntersil Corporation
Intersil Corporation

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