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PDF HIP7030A0M Data sheet ( Hoja de datos )
| Número de pieza | HIP7030A0M | |
| Descripción | J1850 8-Bit 68HC05 Microcontroller Emulator Version | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HIP7030A0
PRELIMINARY
April 1994
J1850 8-Bit 68HC05 Microcontroller
Emulator Version
Features
Description
• HIP7030A2 Microcontroller Emulation
- All HIP7030A2 Hardware and Software Features
- Timing and Performance Equivalent to HIP7030A2
• On-Chip Memory
- 176 Bytes of RAM - No ROM
• Full 8K Byte Address Space Available Externally
• Non-Multiplexed External Address and Data Lines
- I/O Memory Interface Matches Industry Standard
EPROM/EEPROMS for True Emulation with Two
Chips
• FS Line Identifies Fetch Cycles for Breakpoint Logic
• -40oC to +125oC Operating Range
• Single 3.0V to 6.0V Supply
• Available in 68 Lead PLCC Packages
The HIP7030A0 Emulator is functionally equivalent to the
HIP7030A2 microcontroller with the addition of external data
bus, address bus, and control signals which provide off chip
address capability. It is designed to permit prototype and
pre-production development of systems for mask pro-
grammed applications. The HIP7030A0 is also intended for
construction of development systems for the HIP7030A2.
Ordering Information
PART NUMBER
HIP7030A0M
TEMPERATURE
RANGE
-40oC to +125oC
PACKAGE
68 Lead Plastic LCC
Pinout
HIP7030A0 (PLCC)
TOP VIEW
NC
NC
WE
DS
ALC
PD4
PD3
PD2
PD1
PD0
NC
NC
VSS
OSCOUT
OSCIN
SCK
MOSI
9 8 7 6 5 4 3 2 1 6867666564636261
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
2728293031323334353637383940414243
A12
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OSCB
PA0
PA1
PA2
PA3
PA4
PA5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207 | Copyright © Intersil Corporation 1999
9-40
File Number 3645
1 page  
Specifications HIP7030A0
Read Cycle Timing (ALC = 1) (See Figure 3) VDD = 5VDC ±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
MIN
MAX
UNITS
(1)
tCYC
Read Cycle Time
200 -
ns
(2)
tRDOSC
RD, FS Setup Time Before OSCB
0.5tCYC-25
-
ns
(3)
tDVCEL
Access Time From CE
-
tCYC-80
ns
(4)
tDVOSC
Access Time From OSCB
-
tCYC-70
ns
(5)
tOSCAV
Address Setup Time Before OSCB
0.5tCYC-25
-
ns
(6)
tOSCAX
Address Hold Time After OSCB
0.5tCYC
-
ns
(7)
tOSCAX
Data Hold Time After OSCB
10 - ns
Data Bus Driven From CE
(8)
tRDLDX
(Time to Data Active from High Impedance
0
State)
-
ns
(9)
tOSCRD
RD, FS Hold Time After OSCB
(10)
tOSCDS
OSCB to DS Propagation Delay
NOTE:
1. Minimum frequency applies when ALC is high.
0.5tCYC
5
-
25
ns
ns
Write Cycle Timing (ALC = 1) (See Figure 4) VDD = 5VDC ±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
MIN
MAX
UNITS
fOSC
OSCB Operating Frequency
10 MHz
(1)
tCYC
Write Cycle Time
200 -
ns
(2)
tRDOSC
RD, FS Setup Time Before OSCB
0.5tCYC-25
-
ns
(3)
tDVOSC
Data Setup Time Before OSCB
0.75tCYC-95
ns
(4)
tOSCAV
Address Setup Time Before OSCB
0.5tCYC-25
-
ns
(5)
tOSCAX
Address Hold Time After OSCB
0.5tCYC
-
ns
(6)
tOSCAX
Data Hold Time After OSCB
10 - ns
(7)
tOSCDX
Data Bus Driven From OSCB
.25tCYC-25
-
(Time to Data Active from High Impedance
State)
ns
(8)
tOSCRD
RD, FS Hold Time After OSCB
(9)
tOSCDS
OSCB to DS Propagation Delay
NOTE:
1. Minimum frequency applies when ALC is high.
0.5tCYC
5
-
25
ns
ns
9-44
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