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HMP151F7EFR4C-S6D3 PDF даташит

Спецификация HMP151F7EFR4C-S6D3 изготовлена ​​​​«Hynix» и имеет функцию, называемую «240pin Fully Buffered DDR2 SDRAM DIMMs».

Детали детали

Номер произв HMP151F7EFR4C-S6D3
Описание 240pin Fully Buffered DDR2 SDRAM DIMMs
Производители Hynix
логотип Hynix логотип 

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HMP151F7EFR4C-S6D3 Даташит, Описание, Даташиты
240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver.
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point
Link Interface at 1.5V power.
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other
FBDIMMs on the memory channel.
FEATURES
• 240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module
• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
• Built with 1Gb DDR2 SDRAMs in 60ball FBGA
• Host interface and AMB component industry standard compliant
• MBIST, IBIST test functions
• 8 Bank architecture
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• 133.35 x 30.35 mm form factor
• RoHS compliant
• Full DIMM Heat Spreader
This document is a general product description and is subject to change without notice. Hynix Electronics does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Sep. 2008
1
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HMP151F7EFR4C-S6D3 Даташит, Описание, Даташиты
1240pin Fully Buffered DDR2 SDRAM DIMMs
ORDERING INFORMATION
Part Name
HMP112F7EFR8C-Y5N3
HMP112F7EFR8C-Y5/S5/S6D3
HMP112F7EFR8C-Y5/S5/S6D5
HMP125F7EFR8C-Y5N3
HMP125F7EFR8C-Y5/S5/S6D3
HMP125F7EFR8C-Y5/S5/S6D5
HMP151F7EFR4C-Y5N3
HMP151F7EFR4C-Y5/S5/S6D3
HMP151F7EFR4C-Y5/S5/S6D5
HMP151F7EFR8C-Y5/S5/S6D5
HMP31GF7EMR4C-Y5/S5/S6D5
Density
1GB
2GB
4GB
4GB
8GB
Org.
128Mx72
256Mx72
512Mx72
512Mx72
1Gx72
# of
DRAMs
9
18
36
36
72
# of
ranks
1
2
2
4
4
AMB
H. S type Height
Vendor Version
Intel
IDT
Intel
IDT
Intel
IDT
IDT
D1
C1
AMB+
D1
C1
AMB+
D1
C1
AMB+
AMB+
AMB+
Full
Module
30.35mm
Note
*: The 17th and 18th digits stand for AMB vendor and revision.
**: ‘R’ of Part Number;11th digit, stands for lead & Halogen free products.
***: Intel AMB for H/F is under development
SPEED GRADE & KEY PARAMETERS
Speed Grade
DDR2 DRAM Speed Grade
FB-DIMM Speed Grade
FB-DIMM Peak Channel Throughput
FB-DIMM Link Transfer Rate
Y5
DDR2 667 5-5-5
PC2 5300
8.0
4.0
S5/6
DDR2 800 5-5-5 / 6-6-6
PC2 6400
9.6
4.8
Unit
GByte/S
GT/s
ADDRESS TABLE
Density
1GB
2GB
4GB
4GB
8GB
Organization
128M x 72
256M x 72
512M x 72
512M x 72
1G x 72
Ranks
1
2
2
4
4
SDRAMs
128Mbx8
128Mbx8
256Mbx4
128Mbx8
256Mbx4
# of
DRAMs
9
18
36
36
72
# of row/bank/column Address
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
Rev. 0.2 / Sep. 2008
2
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HMP151F7EFR4C-S6D3 Даташит, Описание, Даташиты
1240pin Fully Buffered DDR2 SDRAM DIMMs
Input/Output Functional Description
Pin Name
SCK
SCK
PN[13:0]
PN[13:0]
PS[9:0]
PS[9:0]
SN[13:0]
SN[13:0]
SS[9:0]
SS[9:0]
SCL
SDA
SA[2:0]
type
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
Input
Input / Output
Input
VID[1:0]
Input
RESET
RFU
VCC
VDD
VTT
VDDSPD
VSS
Input
-
Supply
Supply
Supply
Supply
Supply
DNU/M_Test - / Analog
Polarity
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
-
-
-
-
Active Low
-
+1.5V
+1.8V
+0.9V
+3.3V
- / 0.9V
Function Description
Count
System clock input
1
System clock input
1
Primary Northbound Data
14
Primary Northbound Data
14
Primary Southbound Data
10
Primary Southbound Data
10
Secondary Northbound Data
14
Secondary Northbound Data
14
Secondary Southbound Data
10
Secondary Southbound Data
10
Serial Presence Detect (SPD) Clock Input
1
SPD Data Input / Output
1
SPD Address inputs, also used to select the DIMM number in the AMB
3
Voltage ID: These pins must be unconnected for DDR2-based Fully buff-
ered DIMMs
2
AMB reset signal
1
Reserved for Future Use
16
AMB Core Power and AMB channel Interface Power(1.5volt)
8
DRAM Power and AMB DRAM I/O Power
24
DRAM Address/Command/Clock Termination Power(VDD/2)
4
SPD Power
1
Ground
80
The DNU/M_Test pin provides an external connection on R/Cs A-D for
testing the margin of Vref which is produced by a voltage divider on the
module. It is not intended to be used in normal system operation and
must not be connected(DNU) in a system. This test pin may have other
features on future card designs and if it does, will be included in this
specification at that time.
1
Total
240
Rev. 0.2 / Sep. 2008
3
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