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HMP125S6EFR8C-S5 PDF даташит

Спецификация HMP125S6EFR8C-S5 изготовлена ​​​​«Hynix» и имеет функцию, называемую «200pin Unbuffered DDR2 SDRAM SO-DIMMs».

Детали детали

Номер произв HMP125S6EFR8C-S5
Описание 200pin Unbuffered DDR2 SDRAM SO-DIMMs
Производители Hynix
логотип Hynix логотип 

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HMP125S6EFR8C-S5 Даташит, Описание, Даташиты
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version E
This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version E based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-
try standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate 2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
• All inputs and outputs are compatible with SSTL_1.8
interface
• Posted CAS
• Programmable CAS Latency 3,4,5, and 6
• OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both
sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60 ball(x8), 84 ball(x16)
FBGA
• 67.60 x 30.00 mm form factor
• RoHS compliant & Halogen-free
* This product is in compliance with the directive pertaining of RoHS
ORDERING INFORMATION
Part Name
HMP164S6EFR6C-C4/Y5/S5/S6
HMP112S6EFR6C-C4/Y5/S5/S6
HMP125S6EFR8C-C4/Y5/S5/S6
Density Organization
512MB
1GB
2GB
64Mx64
128Mx64
256Mx64
# of
DRAMs
4
8
16
# of
ranks
1
2
2
Materials
Halogen free
Halogen free
Halogen free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Dec. 2009
1
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HMP125S6EFR8C-S5 Даташит, Описание, Даташиты
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
SPEED GRADE & KEY PARAMETERS
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
C4
(DDR2-533)
400
533
-
-
4-4-4
Y5
(DDR2-667)
400
533
667
-
5-5-5
S6
(DDR2-800)
-
533
667
800
6-6-6
S5
(DDR2-800)
400
533
800
-
5-5-5
Unit
Mbps
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization Ranks SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
512MB 64M x 64 1 64Mb x 16 4 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
1GB
128M x 64
2
64Mb x 16
8
13(A0~A12)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
2GB
256M x 64
2
128Mb x 8
16
14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
Rev. 0.3 / Dec. 2009
2
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HMP125S6EFR8C-S5 Даташит, Описание, Даташиты
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN DESCRIPTION
Symbol
Type Polarity
Pin Description
CK[1:0], CK[1:0]
Input
Cross
Point
The system clock inputs. All address an commands lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to
the input clock.
CKE[1:0]
Input
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
S[1:0]
Input
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
RAS, CAS, WE
Input
Active
Low
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,
RAS and WE define the operation to be executed by the SDRAM.
BA[2:0]
Input
Selects which DDR2 SDRAM internal bank of four or eight is activated.
ODT[1:0]
Input
Active
High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
A[9:0], A10/AP,
A[15:11]
Input
During a Bank Activate command cycle, difines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is
high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP
is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in
conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn
are used to define which bank to precharge.
DQ[63:0]
In/Out
Data Input/Output pins.
DM[7:0]
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
DQS[7:0], DQS[7:0] In/Out
Cross
point
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading
edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS. If the module is to be operated in single ended
strobe mode, all DQS signals must be tied on the system board to VSS and DDR2
SDRAM mode registers programmed approriately.
VDD, VDDSPD,VSS
Supply
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
SDA
In/Out
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to VDD to act as a pull up.
SCL
Input
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to VDD to act as a pull up.
SA[1:0]
Input
Address pins used to select the Serial Presence Detect base address.
TEST
In/Out
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules (SODIMMs).
Rev. 0.3 / Dec. 2009
3
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