PDF HFA3524IA96 Data sheet ( Hoja de datos )

Número de pieza	HFA3524IA96
Descripción	2.5GHz/600MHz Dual Frequency Synthesizer
Fabricantes	Intersil Corporation
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No Preview Available ! TM Data Sheet HFA3524 March 2000 File Number 4062.8 2.5GHz/600MHz Dual Frequency Synthesizer The Intersil 2.4GHz PRISM® chip set is a highly integrated six-chip solution for RF modems employing Direct Sequence Spread Spectrum (DSSS) signaling. The HFA3524 600MHz Dual Frequency Synthesizer is one of the six chips in the PRISM chip set (see the Typical Application Diagram). The HFA3524 is a monolithic, integrated dual frequency synthesizer, including prescaler, is to be used as a local oscillator for RF and ﬁrst IF of a dual conversion transceiver. The HFA3524 contains a dual modulus prescaler. A 32/33 or 64/65 prescaler can be selected for the RF synthesizer and a 8/9 or a 16/17 prescaler can be selected for the IF synthesizer. Using a digital phase locked loop technique, the HFA3524 can generate a very stable, low noise signal for the RF and IF local oscillator. Serial data is transferred into the HFA3524 via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The HFA3524 features very low current consumption of 13mA at 3V. Functional Block Diagram fIN IF IF PRESCALER 15-BIT IF N COUNTER OSCIN OSC fIN RF RF PRESCALER 15-BIT IF R COUNTER 15-BIT RF R COUNTER 18-BIT RF N COUNTER Features • 2.7V to 5.5V Operation • Low Current Consumption • Selectable Powerdown Mode ICC = 1µA Typical at 3V • Dual Modulus Prescaler, 32/33 or 64/65 • Selectable Charge Pump High Z State Mode Applications • Systems Targeting IEEE 802.11 Standard • PCMCIA Wireless Transceiver • Wireless Local Area Network Modems • TDMA Packet Protocol Radios • Part 15 Compliant Radio Links • Portable Battery Powered Equipment Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HFA3524IA HFA3524IA96 -40 to 85 -40 to 85 20 Ld TSSOP M20.173 Tape and Reel PHASE COMP IF LD CHARGE PUMP RF LD PHASE COMP CHARGE PUMP DO IF f OUT LOCK DETECT FASTLOCK MUX FO/LD DO RF CLOCK DATA LE 22-BIT DATA REGISTER 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Intersil and Design is a trademark of Intersil Corporation. \| Copyright © Intersil Corporation 2000 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. 1 page HFA3524 Absolute Maximum Ratings Power Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Voltage on Any Pin with GND = 0V (VI) . . . . . . . . . . . -0.3V to +6.5V Operating Conditions Thermal Information Thermal Resistance (Typical, Note 3) θJA (oC/W) TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Storage Temperature Range (TS) . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 4s) (TL) . . . . . . . . . .260oC (TSSOP - Lead Tips Only) Power Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V VP . . . . . . . Temperature .... (TA) . . . . . . .... ... . . . . . . . . . . ..... .... . . . . . . . . . . .... ... . . . . . . . . . . .-.4V0CoCCtoto+855.5oCV CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Speciﬁcations VCC = 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Speciﬁed HFA3524 PARAMETER SYMBOL TEST CONDITIONS MIN TYP Power Supply Current RF + IF RF Only Powerdown Current Operating Frequency Operating Frequency Oscillator Frequency Maximum Phase Detector Frequency ICC ICC-PWDN fIN RF fIN IF fOSC fφ VCC = 2.7V to 5.5V VCC = 2.7V to 5.5V VCC = 3.0V - 13 - 10 -1 0.5 - 45 - 5- 10 - RF Input Sensitivity PfIN RF VCC = 3.0V VCC = 5.0V IF Input Sensitivity PfIN IF VCC = 2.7V to 5.5V Oscillator Sensitivity VOSC OSCIN High Level Input Voltage VIH (Note) Low Level Input Voltage VIL (Note) High Level Input Current IIH VIH = VCC = 5.5V (Note) Low Level Input Current IIL VIL = 0V, VCC = 5.5V (Note) Oscillator Input Current IIH VIH = VCC = 5.5V Oscillator Input Current IIL VIL = 0V, VCC = 5.5V High Level Output Voltage VOH IOH = -500µA High Level Output Voltage VOH IOH = -1mA Low Level Output Voltage VOL IOL = 500µA Low Level Output Voltage VOL IOL = 1mA Data to Clock Set Up Time tCS See Data Input Timing Data to Clock Hold Time tCH See Data Input Timing Clock Pulse Width High tCWH See Data Input Timing Clock Pulse Width Low tCWL See Data Input Timing Clock to Load Enable Set Up Time tES See Data Input Timing Load Enable Pulse Width tEW See Data Input Timing NOTE: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN. -15 -10 -10 0.5 0.8VCC - -1.0 -1.0 - -100 VCC -0.4 - - - 50 10 50 50 50 50 - - - - - - - - - - - - - - - - - - - - MAX - - 25 2.5 600 44 - +4 +4 +4 - - 0.2VCC 1.0 1.0 100 - - - 0.4 - - - - - - - UNITS mA mA µA GHz MHz MHz MHz dBm dBm dBm VP-P V V µA µA µA µA V V V V ns ns ns ns ns ns 5 5 Page HFA3524 TABLE 2. MODE SELECT TRUTH TABLE ΦD POLARITY DO HIGH Z STATE 0 Negative Normal Operation (NOTE 16) ICPO LOW IF PRESCALER 8/9 RF PRESCALER 32/33 (NOTE 17) POWERDOWN Powered Up 1 Positive High Z State HIGH 16/17 64/65 Powered Down NOTES: 16. The ICPO LOW current state = 1/4 x ICPO HIGH current. 17. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF and RF powerdown bits are activated. The OSCIN pin reverts to a high im- pedance state when this condition exists. The control register remains active and capable of loading and latching in data during all of the pow- erdown modes. RF R [19] (RF LD) 0 TABLE 3. THE FO/LD (PIN 10) OUTPUT TRUTH TABLE IF R [19] (IF LD) RF R [20] (RF FO) IF R [20] (IF FO) FO OUTPUT STATE 0 0 0 Disabled (Note 18) 0 1 0 0 IF Lock Detect (Note 19) 1 0 0 0 RF Lock Detect (Note 19) 1 1 0 0 RF/IF Lock Detect (Note 19) X 0 0 1 IF Reference Divider Output X 0 1 0 RF Reference Divider Output X 1 0 1 IF Programmable Divider Output X 1 1 0 RF Programmable Divider Output 0 0 1 1 Fastlock (Note 20) 0 1 1 1 For Internal Use Only 1 0 1 1 For Internal Use Only 1 1 1 1 For Internal Use Only 1 1 1 1 Counter Reset (Note 21) X = Don’t care condition NOTES: 18. When the FO/LD output is disabled, it is actively pulled to a low logic state. 19. Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked. 20. The Fastlock mode utilizes the FO/LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock). 21. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated, the R counter is also forced to Reset, allowing smooth acquisition upon powering up. Phase Detector Polarity Depending upon VCO characteristics, R16 bit should be set accordingly, (see Figure 15). • When VCO characteristics are positive like (1), R16 should be set HIGH. • When VCO characteristics are negative like (2), R16 should be set LOW. (1) (2) VCO INPUT VOLTAGE FIGURE 15. VCO CHARACTERISTICS 11 11 Page

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