|
|
PDF HFA3783 Data sheet ( Hoja de datos )
| Número de pieza | HFA3783 | |
| Descripción | I/Q Modulator/Demodulator and Synthesizer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HFA3783 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
TM
Data Sheet
HFA3783
March 2000 File Number 4633.2
I/Q Modulator/Demodulator and
Synthesizer
The HFA3783 is a highly integrated and
fully differential SiGe baseband
converter for half duplex wireless
applications. It features all the
necessary blocks for quadrature
modulation and demodulation of “I” and “Q” baseband
signals.
It has an integrated AGC receive IF amplifier with frequency
response to 600MHz. The AGC has 70dB of voltage gain
and better than 70dB of gain control range. The transmit
output also features gain control with 70dB of range.
The receive and transmit IF paths can share a common
differential matching network to reduce the filter component
count required for single IF half duplex transceivers. A pair of
2nd order antialiasing filters with an integrated DC offset
cancellation architecture is included in the receive chain for
baseband operation down to DC. In addition, an IF level
detector is included in the AGC chain for threshold
comparison. Up and down conversion are performed by
doubly balanced mixers for “I” and “Q” IF processing. These
converters are driven by a broadband quadrature LO
generator with frequency of operation phase locked by an
internal 3 wire interface synthesizer and PLL.
The device operates at low LO levels from an external VCO
with a PLL reference signal up to 50MHz. The HFA3783 is
housed in a thin 48 lead LQFP package well suited for
PCMCIA board applications.
Simplified Block Diagram
Features
• Integrates All IF Transmit and Receive Functions
• Broad Quadrature Frequency Range . . . . . .70 to 600MHz
• 600MHz AGC IF Strip with Level Detector . . . . . . . . .69dB
• DC Coupled Baseband Interfaces
• Integrates a Receiver DC Offset Calibration Loop
• Integrated 3 Wire Interface PLL For LO Applications
• Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm
• Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . <1µs
• Power Management/Standby Mode
• Single Supply 2.7 to 3.3V Operation
Applications
• IEEE802.11 1 and 2Mbps Standard
• Systems Targeting IEEE 802.11 11Mbps Standard
• Wireless Local Area Networks
• PCMCIA Wireless Transceivers
• ISM Systems
• TDMA Packet Protocol Radios
Ordering Information
PART
NUMBER
HFA3783IN
HFA3783IN96
TEMP. RANGE
(oC)
PACKAGE PKG. NO.
-40 to 85
48 Ld LQFP Q48.7x7A
-40 to 85 Tape and Reel
IF_IN
IF_OUT
IF DETECTOR OUT
RECEIVE AGC
I BASEBAND RXI
OFFSET
CAL
CAL ENABLE
Q BASEBAND RXQ
0o/90oPLL MODULE
IF 2X LO / VCO IN
CHARGE PUMP OUT
3 WIRE INTERFACE
REF IN
∑ BASEBAND TX I
BASEBAND TXQ
TRANSMIT IF AGC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
1 page  
HFA3783
Test Diagram
FREQUENCY RESPONSE TEST SET UP
SWEEP
GEN.
1000p
50
1000p
VCC
50
200p
50
2
3
4
5
6
7
8
9
50
ANALYZER
IF_DET
RX_VAGC
CALIBRATION
5KΩ INPUT
CALIBRATION
RXI
VCC
10µ
.01
.01
RXQ
TX_VAGC
1000p
IF IN/OUT
TC4-1W
100p
100p
.01
8p
2K
8p
1000p
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 LO 31
7 30
8∑
9
29
28
10 27
11
SYNTH 0/90
26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
MATCH COMPONENTS FOR
TEST FIXTURE (374MHz)
AND TRANSFORMER
1000p
1000p
50
.1
.1
VCC/2
5KΩ INPUT
CALIBRATION
1.2V REF.
.1
56p
100p
.1
100p
50
1.2V_OUT
COMMON MODE VOLTAGE
CALIBRATION
COMMON MODE VOLTAGE
LO_IN (2X FREQ)
REF_IN
(SINUSOIDAL)
CP
BUFFER
TXQ
TXI
(LOW INPUT CAPACITANCE)
5
5 Page 
HFA3783
PLL Synthesizer and DC Offset Clock Programming Table (Continued)
REGISTER
DEFINITION
SERIAL
BITS LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
Operational 1
0 M(0) 0 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 0
0
0
0 M(13) M(14) M(15) X X
Mode
Offset
Calibration
1
1 C(0) C(1) C(2) C(3) C(4) C(5) C(6) 0 0 0
0 C(11)
X (Don’t Care)
NOTES:
6. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is
latched into defined registers on the rising edge of LE.
7. The M register or Operational Mode needs to be loaded first. Registers R, A/B and Offset Calibration follow M loading in any sequence.
Reference Frequency Counter/Divider
BIT DESCRIPTION
R(0-14)
Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down
by this counter and is compared with a divided LO by a phase detector.
LO Frequency Counters/Dividers
BIT DESCRIPTION
A(0-6)
B(0-10)
Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11 bits divider.
The LO frequency is divided down by [P*B+A], where P is the prescaler divider set by bit M(2). This divided signal frequency is
compared by a phase detector with the divided Reference signal.
Operational Modes
BIT DESCRIPTION
M(0)
(PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on.
M(2)
Prescaler Select. 0 = 16/17, 1 = 32/33
M(3)
M(4)
Charge Pump Current Setting.
M(4)
0
M(3)
0
OUTPUT SINK/SOURCE
0.25mA
0 1 0.50mA
1 0 0.75mA
1 1 1.00mA
M(5)
M(6)
Charge Pump Sign.
M(7)
M(8)
M(13)
LD Pin Multiplex Operation.
M(6)
0
0
M(13)
0
0
M(5)
0
1
M(8)
0
1
Source Current if LO/ [P*B+A] < Ref/R
Source Current if LO/ [P*B+A] > Ref/R
M(7)
OUTPUT AT PIN LD
X Lock Detect Operation
X Short to GND
10
X Serial Register Read Back
11
0 Ref. Divided by R Waveform
11
1 LO Divided by [P*B+A]
Waveform
M(14)
M(15)
Charge Pump Operation/Test.
M(15)
0
M(14)
0
OPERATION/TEST
Normal Operation
0 1 Charge Pump Constant Current Source
1 0 Charge Pump Constant Current Sink
1 1 High Impedance State
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HFA3783.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HFA3783 | I/Q Modulator/Demodulator and Synthesizer | Intersil Corporation |
| HFA3783IN | I/Q Modulator/Demodulator and Synthesizer | Intersil Corporation |
| HFA3783IN96 | I/Q Modulator/Demodulator and Synthesizer | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |