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PDF HFA3841CN96 Data sheet ( Hoja de datos )
| Número de pieza | HFA3841CN96 | |
| Descripción | Wireless LAN Medium Access Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
PRELIMINARY
Data Sheet
HFA3841
January 2000 File Number 4661.2
Wireless LAN Medium Access Controller
The Intersil HFA3841 Wireless LAN
Medium Access Controller is part of the
PRISM® Enterprise 2.4GHz WLAN
chip set. The HFA3841 directly
interfaces with the Intersil HFA386x
family of Baseband Processors, offering a complete end-to-
end chip set solution for wireless LAN products. Protocol and
PHY support are implemented in firmware to allow custom
protocol and different PHY transceivers.
The HFA3841 is designed to provide maximum performance
with minimum power consumption. External pin layout is
organized to provide optimal PC board layout to all user
interfaces.
Firmware implements the full IEEE 802.11 Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgement, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handed without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.
Designing wireless protocol systems using the HFA3841 is
made easier with the availability of evaluation board,
firmware, software device drivers, and complete
documentation.
Features
• IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps
• Part of the Intersil PRISM Wireless LAN Chip Set
• Full Implementation of the MAC Protocol Specified in
IEEE Std. 802.11-1999 and the 802.11b Draft Standard
• Host Interface Supports Full 16-Bit Implementation of PC
Card 95, also ISA PnP with Additional Chip
• Host Interface Provides Dual Buffer Access Paths
• External Memory Interface Supports up to 4M bytes RAM
• Internal Encryption Engine Executes IEEE802.11 WEP
• Low Power Operation; 25mA Active, 8mA Doze, <1mA Sleep
• Operation at 2.7V to 3.6V Supply
• 3V to 5V Tolerant Input/Outputs
• 128 Pin LQFP Package Targeted for Type II PC Cards
• IEEE802.11 Wireless LAN MAC Protocol Firmware and
Microsoft® Windows® Software Drivers
Applications
• High Data Rate Wireless LAN
• PC Card Wireless LAN Adapters
• ISA, ISA PnP WLAN Cards
• PCI Wireless LAN Cards (Using Ext. Bridge Chip)
• Wireless LAN Modules
• Wireless LAN Access Points
• Wireless Bridge Products
• Wireless Point-to-Multipoint Systems
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG. NO.
HFA3841CN
0 to 70
128 Ld LQFP Q128.14x20
HFA3841CN96
0 to 70
Tape and Reel
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1 Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
1 page  
Preliminary - HFA3841
Power
PIN NAME
PIN NUMBER
PIN I/O TYPE
DESCRIPTION
VCC_CORE3
14, 25, 39, 53
3.3V Core Supply
VCC_IO3
66, 83, 98. 124
3.3V I/O Supply
VCC_IO5
105 5V Tolerance Supply
VSS_CORE3
VSS_IO3
TRST-
13, 24, 37
42, 52, 67, 82, 97, 115
62
Core VSS
I/O VSS
CMOS Input
Reserved - Must be tied low through 1K
ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.
NOTE: Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at
rated loads.
Port Pin Uses for PRISM Application
PIN
20
19
18
17
31
30
32
29
65
8
7
9
35
34
33
63
64
21
22
23
15
27
26
28
43
12
11
93
NAME
RXC
RXD
TXC
TXD
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PRISM I USE
PRISM II™ USE
RXC - Receive clock
RXC - Receive clock
RXD - Receive data
RXD - Receive data
TXC - Transmit clock
TXC - Transmit clock
TXD - Transmit data
TXD - Transmit data
SCLK - Clock for the SD serial bus.
SCLK - Clock for the SD serial bus.
SD - Serial bi-directional data bus
SD - Serial bi-directional data bus
R/W - An input to the HFA3860A used to change Not Used
the direction of the SD bus when reading or writing
data on the SD bus.
CS - A Chip select for the device to activate the se- CS_BAR - Chip select for HFA3861 baseband
rial control port. (active low)
(active low)
Not Used
PE1 - Power Enable 1
SYNTH_LE - Latches a frame of 22 bits after it has LE_IF - Load enable for HFA3783 Quad IF
been shifted by the SCLK into the synthesizer reg-
isters.
LED - Activity indicator
LED - Activity indicator
Not Used
RADIO_PE - RF power enable
Not Used
LE_RF - Load enable for HFA3983 RF chip
Not Used
SYNTHCLK - Serial clock to front end chips
Not Used
SYNTHDATA - Serial data to front end chips
TX_PE_RF - Power Enable
PA_PE - Transmit PA power enable
RX_PE_RF - Power Enable
PE2 - Power Enable 2
MD_RDY - Header data and data packet are ready MDREADY - Header data and data packet are
to be transferred from Baseband on RXD
ready to be transferred from Baseband on RXD
CCA - Signal that the channel is clear to transmit. CCA - Signal that the channel is clear to transmit.
RADIO_PE - Master power control for the RF
section
CAL_EN - Calibration mode enable
TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband
RX_PE - Receive Enable to Baseband
RX_PE - Receive Enable to Baseband
RESET - Reset to Baseband
RESET_BB - Reset Baseband
Not Used
T/R-SW_BAR - Transient/Receive Control (Inverted)
MA19 (if required)
MA19 (if required)
MA20 (if required)
MA20 (if required)
MA21 (if required)
Reserved
TX_RDY - Baseband ready to receive data on TXD T/R_SW - Transmit/Receive Control
(not used by firmware)
5
5 Page 
Preliminary - HFA3841
Waveforms (Continued)
OSC
44MHz
23ns
MCLK
(INTERNAL)
QCLK
(INTERNAL)
10ns (NOTE 12)
14.67MHz
68.2ns
10ns
(NOTE 12)
10ns (NOTE 12)
MCLKOUT
ADDRESS,
RAMCS_
MOE_
MD0-15
READ DATA
11.5ns
17ns
17ns
24ns
VALID DATA AT MDIN
tH≥0
MWEH/L_
MD0-15
WRITE DATA
13ns
16ns
20ns
VALID DATA
tH≥0
MBUS READ CYCLE
MBUS WRITE CYCLE
NOTES:
11. 14.67MHz requires an odd divisor in the prescaler. Note that both edges of OSC are used to create MCLK and QCLK, thus a deviation from
50% duty cycle in OSC will result in corresponding changes in MBUS timing.
12. Timing delays between OSC and internal clocks are shown for information purposes only.
FIGURE 3. MBUS MEMORY TIMING - 14.67MHz MCLK
MCLK
EMA [15:0]
EMCSxN
EMOEN
EMWRN
EMD [15:0]
11
tD1
tD2
tD1
tD3 tD4
tS1 tH1
FIGURE 4.
tD5
tD6
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet HFA3841CN96.PDF ] | |
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