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PDF HFA3861 Data sheet ( Hoja de datos )
| Número de pieza | HFA3861 | |
| Descripción | Direct Sequence Spread Spectrum Baseband Processor | |
| Fabricantes | Intersil Corporation | |
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ADVANCE INFORMATION Data Sheet
HFA3861
July 1999 File Number 4699.1
Direct Sequence Spread Spectrum
Baseband Processor
™ The Intersil HFA3861 Direct Sequence
Spread Spectrum (DSSS) baseband
processor is part of the PRISM®
2.4GHz radio chipset, and contains all
the functions necessary for a full or half duplex packet
baseband transceiver.
The HFA3861 has on-board A/D’s for analog I and Q inputs
and outputs, for which the HFA3783 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSK and DQPSK, with data scrambling
capability, are available along with Complementary Code
Keying to provide a variety of data rates. Built-in flexibility
allows the HFA3861 to be configured through a general
purpose control bus, for a range of applications. Both
Receive and Transmit AGC functions with 7-bit AGC control
obtain maximum performance in the analog portions of the
transceiver. The HFA3861 is housed in a thin plastic quad
flat package (TQFP) suitable for PCMCIA board
applications.
Ordering Information
PART NO.
HFA3861IV
HFA3861IV96
TEMP.
RANGE (oC)
-40 to 85
-40 to 85
PKG. TYPE
64 Ld TQFP
Tape and Reel
PKG. NO.
Q64.10x10
Pinout
Features
• Complete DSSS Baseband Processor
• Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant
• Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps
• Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm
• Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V
• Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK
• Supports Full or Half Duplex Operations
• On-Chip A/D and D/A Converters for I/Q Data (6-Bit,
22MSPS), AGC, and Adaptive Power Control (7-Bit)
• Targeted for Multipath Delay Spreads ~100ns
• Supports Short Preamble Acquisition
Applications
• Enterprise WLAN Systems
• Systems Targeting IEEE 802.11 Standard
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable PDA/Notebook Computer
• Wireless Digital Audio, Video, Multimedia
• PCN/Wireless PBX
• Wireless Bridges
GNDd
VDDD
SD
SCLK
R/W
CS
GNDd
VDDD
GNDa
RX_I+
RX_I-
VDDA
RX_Q+
RX_Q-
GNDa
VREF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TEST4
TEST3
TEST2
TEST1
TEST0
GNDd
MCLK
NC
ANT-SEL
ANT-SEL
RX-RF_AGC
VDDD
GNDd
TX_IF_AGC
RX_IF_AGC
COMPCAP1
Simplified Block Diagram
ANT_SEL
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
THRESH.
DETECT
IF
DAC
RX_I±
RX_Q±
VREF
I ADC
Q ADC
1
1
7
6
6
TX_I±
TX_Q±
I DAC
Q DAC
6
6
AGC
CTL
DEMOD
DATA I/O
I/O
MOD
TX_IF_AGC
TX_AGC_IN
44MHz MCLK
TX
DAC
TX
ADC
7 TX
ALC
6
HFA 3861 BBP
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
PRISM and PRISM logo are trademarks of Intersil Corporation.
1 page  
HFA3861
Pin Descriptions (Continued)
NAME
MD_RDY
PIN
54
RX_PE
SD
61
3
SCLK
4
SDI 64
R/W 5
CS 6
TEST 7:0
RESET
51, 50, 49,
48, 47, 46,
45, 44
63
MCLK
42
TXI+/-
TXQ+/-
23/24
29/30
CompCap
33
CompCap2
26
CompRes1
32
CompRes2
27
NOTE: See CR10<3>.
TYPE I/O
DESCRIPTION
O MD_RDY is an output signal to the network processor, indicating header data and a data packet are
ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data
transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns
to its inactive state when RX_PE goes inactive or an error is detected in the header.
I When active, the receiver is configured to be operational, otherwise the receiver is in standby mode.
This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled.
I/O SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal
registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the
register address immediately followed by 8 more bits representing the data that needs to be written
or read at that register. In the 4 wire interface mode, this pin is tristated unless the R/W pin is high.
I SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input
clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is
11MHz or one half the master clock frequency, whichever is lower.
I Serial Data Input in 3 wire mode described in Tech Brief TBD. This pin is not used in the 4 wire
interface described in this data sheet. It should not be left floating.
I R/W is an input to the HFA3861 used to change the direction of the SD bus when reading or writing
data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read
while a low level is a write.
I CS is a Chip select for the device to activate the serial control port. The CS doesn’t impact any of the
other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low
signal. When inactive SD, SCLK, and R/W become “don’t care” signals.
I/O This is a data port that can be programmed to bring out internal signals or data for monitoring. These
bits are primarily reserved by the manufacturer for testing. A further description of the test port is given
in the appropriate section of this data sheet.
I Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3861 goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up.
I Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to
generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
O TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/ 24-
O TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-.
I Compensation capacitor
I Compensation capacitor
I Compensation Resistor
I Compensation Resistor
External Interfaces
There are three primary digital interface ports for the
HFA3861 that are used for configuration and during normal
operation of the device as shown in Figure 1. These ports
are:
• The Control Port, which is used to configure, write
and/or read the status of the internal HFA3861
registers.
• The TX Port, which is used to accept the data that
needs to be transmitted from the network processor.
• The RX Port, which is used to output the received
demodulated data to the network processor.
In addition to these primary digital interfaces the device
includes a byte wide parallel Test Port which can be
configured to output various internal signals and/or data.
The device can also be set into various power consumption
modes by external control. The HFA3861 contains four
Analog to Digital (A/D) converters and four Digital to Analog
converters. The analog interfaces to the HFA3861 include,
the In phase (I) and quadrature (Q) data component inputs/
outputs, and the RF and IF receive automatic gain control
and transmit output power control.
5
5 Page 
HFA3861
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1's
(before entering the scrambler) plus a start frame delimiter
(SFD). The actual transmitted pattern of the preamble is
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform (1Mbps). The duration of
the long preamble and header is 192µs.
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at
2Mbps. The synchronization preamble is all 0’s to distinguish
it from the long header mode and the short preamble SFD is
the time reverse of the long preamble SFD. The duration of
the short preamble and header is 96µs.
Start Frame Delimiter (SFD) Field (16 Bits) - This field is
used to establish the link frame timing. The HFA3861 will not
declare a valid data packet, even if it PN acquires, unless it
detects the SFD. The HFA3861 receiver is programmed to
time out searching for the SFD via CR 10 BITS 4 and 5. The
timer starts counting the moment that initial PN
synchronization has been established on the preamble.
The four fields for the header shown in Figure 8 are:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The HFA3861
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
fields.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. These bits are not used by the HFA3861.
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits)- This field includes the 16-bit
CCITT - CRC 16 calculation of the three header fields. This
value is compared with the CCITT - CRC 16 code calculated
at the receiver. The HFA3861 receiver will indicate a CCITT -
CRC 16 error via CR24 bit 2 and will lower MD_RDY and
reset the receiver to the acquisition mode if there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x16 + x12 + x5 + 1
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR 4 - Defines the preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of
128d = 80h.
CR 10 bits 4,5 - Define the length of time that the
demodulator searches for the SFD before returning to
acquisition.
CR 5 bits 0,1 - These bits of the register set the Signal field
to indicate what modulation is to be used for the data portion
of the packet.
CR 6 - The value to be used in the Service field.
CR 7 and 8 - Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol and is in microseconds required to
transmit the data at the chosen data rate.
The packet consists of the preamble, header and MAC
protocol data unit (MPDU). The data is transmitted exactly
as received from the control processor. Some dummy bits
will be appended to the end of the packet to insure an
orderly shutdown of the transmitter. This prevents spectrum
splatter. At the end of a packet, the external controller is
expected to de-assert the TX_PE line to shut the
transmitter down.
PREAMBLE (SYNC) SFD
128/56 BITS
16 BITS
PREAMBLE
SIGNAL FIELD
8 BITS
SERVICE FIELD LENGTH FIELD CRC16
8 BITS
16 BITS
16 BITS
HEADER
FIGURE 8. 802.11 PREAMBLE/HEADER
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HFA3861.PDF ] | |
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