PDF HFA3861BIN Data sheet ( Hoja de datos )

Número de pieza	HFA3861BIN
Descripción	Direct Sequence Spread Spectrum Baseband Processor
Fabricantes	Intersil Corporation
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No Preview Available ! TM Data Sheet February 2002 HFA3861B FN4816.2 Direct Sequence Spread Spectrum Baseband Processor The Intersil HFA3861B Direct Sequence Spread Spectrum (DSSS) baseband processor is part of the PRISM® 2.4GHz WLAN Chip Set, and contains all the functions necessary for a full or half duplex packet baseband transceiver. The HFA3861B has on-board A/D’s and D/A for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates. Built-in ﬂexibility allows the HFA3861B to be conﬁgured through a general purpose control bus, for a range of applications. Both Receive and Transmit AGC functions with 7-bit AGC control obtain maximum performance in the analog portions of the transceiver. The HFA3861B is housed in a thin plastic quad ﬂat package (TQFP) suitable for PCMCIA board applications. Ordering Information PART NUMBER HFA3861BIN HFA3861BIN96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 64 Ld TQFP Tape and Reel PKG. NO. Q64.10x10 Pinout GNDd VDDD SD SCLK R/W CS GNDd VDDD GNDa RX_I+ RX_I- VDDA RX_Q+ RX_Q- GNDa VREF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TEST4 TEST3 TEST2 TEST1 TEST0 GNDd MCLK NC ANT-SEL ANT-SEL RX-RF_AGC VDDD GNDd TX_IF_AGC RX_IF_AGC COMPCAP1 Features • Complete DSSS Baseband Processor • Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant • Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps • Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm • Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V • Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK • Supports Full or Half Duplex Operations • On-Chip A/D and D/A Converters for I/Q Data (6-Bit, 22MSPS), AGC, and Adaptive Power Control (7-Bit) • Targeted for Multipath Delay Spreads ~50ns • Supports Short Preamble Acquisition • Supports Antenna Diversity Applications • Enterprise WLAN Systems • Systems Targeting IEEE 802.11 Standard • DSSS PCMCIA Wireless Transceiver • Spread Spectrum WLAN RF Modems • TDMA Packet Protocol Radios • Part 15 Compliant Radio Links • Portable PDA/Notebook Computer • Wireless Digital Audio, Video, Multimedia • PCN/Wireless PBX • Wireless Bridges Simpliﬁed Block Diagram ANT_SEL RX_RF_AGC RX_IF_DET RX_IF_AGC THRESH. DETECT IF DAC RX_I± RX_Q± VREF I ADC Q ADC 1 1 7 6 6 TX_I± TX_Q± I DAC Q DAC 6 6 AGC CTL DEMOD DATA I/O I/O MOD TX_IF_AGC TX_AGC_IN 44MHz MCLK TX DAC TX ADC 7 TX ALC 6 HFA 3861B BBP 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved PRISM® is a registered trademark of Intersil Corporation. PRISM and design is a trademark of Intersil Corporation. 1 page HFA3861B ANALOG INPUTS A/D REFERENCE POWER DOWN SIGNALS TEST PORT ANT_SEL HFA3861B RXI RXQ AGC AGC TXI TXQ VREF IREF TX_PE RX_PE RESET 8 TEST TXD TXCLK TX_RDY RXD RXC MD_RDY CS SD SCLK R/W SDI ANALOG OUTPUTS TX_PORT RX_PORT CONTROL_PORT FIGURE 1. EXTERNAL INTERFACES Control Port (4 Wire) The serial control port is used to serially write and read data to/from the device. This serial port can operate up to a 11MHz rate or 1/2 the maximum master clock rate of the device, MCLK (whichever is lower). MCLK must be running and RESET must be inactive during programming. This port is used to program and to read all internal registers. The ﬁrst 8 bits always represent the address followed immediately by the 8 data bits for that register. The LSB of the address is a don’t care, but reserved for future expansion. The serial transfers are accomplished through the serial data pin (SD). SD is a bidirectional serial data bus. Chip Select (CS), and Read/Write (R/W) are also required as handshake signals for this port. The clock used in conjunction with the address and data on SD is SCLK. This clock is provided by the external source and it is an input to the HFA3861B. The timing relationships of these signals are illustrated in Figures 2 and 3. R/W is high when data is to be read, and low when it is to be written. CS is an asynchronous reset to the state machine. CS must be active (low) during the entire data transfer cycle. CS selects the serial control port device only. The serial control port operates asynchronously from the TX and RX ports and it can accomplish data transfers independent of the activity at the other digital or analog ports. The HFA3861B has 96 internal registers that can be conﬁgured through the control port. These registers are listed in the Conﬁguration and Control Internal Register table. Table 9 lists the conﬁguration register number, a brief name describing the register, the HEX address to access each of the registers and typical values. The type indicates whether the corresponding register is Read only (R) or Read/Write (R/W). Some registers are two bytes wide as indicated on the table (high and low bytes). SCLK SD FIRST ADDRESS BIT FIRST DATABIT OUT 7 6 5 4 3 2 1 07 6 5 4 3 2 1 0 7654321 MSB ADDRESS IN 7654321 0 MSB DATA OUT LSB R/W CS NOTES: 1. The HFA3861B always uses the rising edge of SCLK to sample address and data and to generate read data. 2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data. FIGURE 2. CONTROL PORT READ TIMING SCLK SD R/W CS 7654321076543 210 76 54 3 21 0765 4 3 21 0 MSB ADDRESS IN MSB DATA IN LSB FIGURE 3. CONTROL PORT WRITE TIMING 5 5 Page HFA3861B Scrambling is done by a division using a prescribed polynomial as shown in Figure 9. A shift register holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift register. The taps are programmable. The transmit scrambler seed for the long preamble or for the short preamble can be set with CR36 or CR37. SERIAL DATA IN XOR Z-1 Z-2 Z-3 Z-4 SERIAL DATA OUT Z-5 Z-6 Z-7 XOR FIGURE 9. SCRAMBLING PROCESS For the 1Mbps DBPSK data rates and for the header in all rates, the data coder implements the desired DBPSK coding by differential encoding the serial data from the scrambler and driving both the I and Q output channels together. For the 2Mbps DQPSK data rate, the data coder implements the desired coding as shown in the DQPSK Data Encoder table. This coding scheme results from differential coding of dibits (2 bits). Vector rotation is counterclockwise although bits 6 and 7 of conﬁguration register CR 1 can be used to reverse the rotation sense of the TX or RX signal if desired. TABLE 4. DQPSK DATA ENCODER PHASE SHIFT DIBIT PATTERN (d0, d1) d0 IS FIRST IN TIME 0 00 +90 01 +180 11 -90 10 Spread Spectrum Modulator Description The modulator is designed to generate DBPSK, DQPSK, and CCK spread spectrum signals. The modulator is capable of automatically switching its rate where the preamble is DBPSK modulated, and the data and/or header are modulated differently. The modulator can support date rates of 1, 2, 5.5 and 11Mbps. The programming details to set up the modulator are given at the introductory paragraph of this section. The HFA3861B utilizes Quadraphase (I/Q) modulation at baseband for all modulation modes. In the 1Mbps DBPSK mode, the I and Q Channels are connected together and driven with the output of the scrambler and differential encoder. The I and Q Channels are then both multiplied with the 11-bit Barker word at the spread rate. The I and Q signals go to the Quadrature upconverter (HFA3724) to be modulated onto a carrier. Thus, the spreading and data modulation are BPSK modulated onto the carrier. For the 2Mbps DQPSK mode, the serial data is formed into dibits or bit pairs in the differential encoder as detailed above. One of the bits from the differential encoder goes to the I Channel and the other to the Q Channel. The I and Q Channels are then both multiplied with the 11-bit Barker word at the spread rate. This forms QPSK modulation at the symbol rate with BPSK modulation at the spread rate. Transmit Filter Description To minimize the requirements on the analog transmit ﬁltering, the transmit section shown in Figure 11 has an output digital ﬁlter. This ﬁlter is a Finite Impulse Response (FIR) style ﬁlter whose shape is set by tap coefﬁcients. This ﬁlter shapes the spectrum to meet the radio spectral mask requirements while minimizing the peak to average amplitude on the output. To meet the particular spread spectrum processing gain regulatory requirements in Japan, an extra FIR ﬁlter shape has been included that has a wider main lobe. This increases the 90% power bandwidth from about 11MHz to 14MHz. It has the unavoidable side effect of increasing the amplitude modulation, so the available transmit power is compromised by 2dB when using this ﬁlter (CR 11 bit 5). The receive section Channel Matched Filter (CMF) is also tailored to match the characteristics of the transmit ﬁlter. CCK Modulation The spreading code length is 8 and based on complementary codes. The chipping rate is 11Mchip/s and the symbol duration is exactly 8 complex chips long. The following formula is used to derive the CCK code words that are used for spreading both 5.5 and 11Mbps: c =  e j ( ϕ1 + ϕ2 + ϕ3 + ϕ4), ej(ϕ1 + ϕ3 + ϕ4), j e (ϕ1 + ϕ2 + ϕ4 ) ,  –ej(ϕ1 + ϕ4 ) , j e ( ϕ1 + ϕ2 + ϕ3 ) , e j ( ϕ1 + ϕ3), –e j ( ϕ1 + ϕ2), ejϕ1    (LSB to MSB), where c is the code word. The terms: ϕ1, ϕ2, ϕ3, and ϕ4 are deﬁned below for 5.5Mbps and 11Mbps. This formula creates 8 complex chips (LSB to MSB) that are transmitted LSB ﬁrst. The coding is a form of the generalized Hadamard transform encoding where ϕ1 is added to all code chips, ϕ2 is added to all odd code chips, ϕ3 is added to all odd pairs of code chips and ϕ4 is added to all odd quads of code chips. The phases ϕ1 modify the phase of all code chips of the sequence and are DQPSK encoded for 5.5 and 11Mbps. This will take the form of rotating the whole symbol by the appropriate amount relative to the phase of the preceding symbol. Note that the last chip of the symbol deﬁned above is the chip that indicates the symbol’s phase. 11 11 Page

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