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PDF NT5TU32M16DG Data sheet ( Hoja de datos )
| Número de pieza | NT5TU32M16DG | |
| Descripción | 512Mb DDR2 SDRAM | |
| Fabricantes | Nanya | |
| Logotipo |  |
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NT5TU64M8DE / NT5TU32M16DG
512Mb DDR2 SDRAM
Feature
CAS Latency Frequency
Speed Bins
-3C/3CI*
(DDR2-667-CL5)
Parameter
Min.
Max.
Clock Frequency
125
333
tRCD
15 -
tRP 15 -
tRC 60 -
tRAS
45 70K
tCK(Avg.)@CL3
5
8
tCK(Avg.)@CL4
3.75
8
tCK(Avg.)@CL5
3
8
tCK(Avg.)@CL6
-
-
tCK(Avg.)@CL7
-
-
-AC/ACI*
(DDR2-800-CL5)
Min.
Max.
125 400
12.5 -
12.5 -
57.5 -
45 70K
58
3.75 8
2.5 8
2.5 8
--
-BE*
(DDR2-1066-CL7)
Min.
Max.
125 533
12.5 -
12.5 -
57.5 -
45 70K
58
3.75 8
2.5 8
2.5 8
1.875
8
-BD*
(DDR2-1066-CL6)
Min.
Max.
125 533
11.25
-
11.25
-
56.25
45
5
-
70K
8
3.75 8
2.5 8
1.875
8
1.875
8
Units
tCK(Avg.)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
*The timing specification of high speed bin is backward compatible with low speed bin
z 1.8V ± 0.1V Power Supply Voltage
z Data-Strobes: Bidirectional, Differential
z 4 internal memory banks
z Support Industrial grade temperature -40 ~95
z Programmable CAS Latency:
Operating Temperature (-3CI/-ACI)
3, 4, 5 (-3C/-3CI/-AC/-ACI/-BD/-BE)
z 1KB page size for x8
6 (-AC/-ACI/-BD/-BE)
2KB page size for x16
7 (-BD/-BE)
z Strong and Weak Strength Data-Output Driver
z Programmable Additive Latency: 0, 1, 2, 3, 4 5
z Auto-Refresh and Self-Refresh
z Write Latency = Read Latency -1
z Power Saving Power-Down modes
z Programmable Burst Length:
z 7.8 µs max. Average Periodic Refresh Interval
z 4 and 8 Programmable Sequential / Interleave Burst
z RoHS Compliance and Halogen Free
z OCD (Off-Chip Driver Impedance Adjustment)
z ODT (On-Die Termination)
z 4 bit prefetch architecture
z Packages:
60-Ball BGA for x8 components
84-Ball BGA for x16 components
REV 1.7
Jul / 2012
CONSUMER DRAM
1
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Free Datasheet http://www.datasheet4u.com/
1 page  
NT5TU64M8DE / NT5TU32M16DG
512Mb DDR2 SDRAM
Input / Output Functional Description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is
referenced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
CKE
Input
Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS is registered high. CS provides for external rank
CS Input
selection on systems with multiple memory ranks. CS is considered part of the command code.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM, LDM, UDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
x8 device, the function of DM or RDQS / RQDS is enabled by EMRS command.
BA0 – BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provides the row address for Activate commands and the column address and
Auto Precharge or Read/Write commands to select one location out of the memory array in the
A0 – A13
Input
respective bank. A10 is sampled during a Precharge command to determine whether the
precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be
precharged, the bank is selected by BA0-BA1. The address inputs also provide the op-code during
Mode Register Set commands.A13 Row address use on x8 components only.
DQ Input/output Data Inputs/Output: Bi-directional data bus.
DQS, (DQS)
LDQS, (LDQS),
UDQS,(UDQS)
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
Input/output
the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide
differential pair signaling to the system during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals.
REV 1.7
Jul / 2012
CONSUMER DRAM
5
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Free Datasheet http://www.datasheet4u.com/
5 Page 
NT5TU64M8DE / NT5TU32M16DG
512Mb DDR2 SDRAM
- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must
be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to
VDDQ.)
- Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ VREF must be met at all time.
- Apply VTT.
2. Start clock (CK, CK) and maintain stable condition.
3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and
maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or
Deselect & take CKE HIGH.
4. Waiting minimum of 400ns then issue pre-charge all command. NOP or Deselect applied during 400ns period.
5. Issue an EMRS command to EMR (2). (Provide LOW to BA0, and HIGH to BA1).
6. Issue an EMRS command to EMR (3). (HIGH to BA0 and BA1).
7. Issue EMRS to enable DLL. (Provide Low to A0, HIGH to BA0 and LOW to BA1 and A13. And A9=A8=A7=LOW must
be used when issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (Provide HIGH to A8 and LOW to BA0 and A13)
9. Issue a precharge all command.
10. Issue 2 more auto-refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without
resetting the DLL.)
12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration
is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit
OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 DRAM is now ready for normal operation.
* To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
Example:
400 ns
NOP
REV 1.7
Jul / 2012
tRP
tMRD
tMRD
EMRS
Extended Mode
Register Set
with DLL enable
MRS
Mode Register Set
with DLL reset
tRP tRFC
min. 200 cycles to
lock the DLL
tRFC
tMRD
Follow OCD
flowchart
Follow OCD
flowchart
CONSUMER DRAM
11
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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