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HI-5042 PDF даташит

Спецификация HI-5042 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Analog Switches».

Детали детали

Номер произв HI-5042
Описание CMOS Analog Switches
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HI-5042 Даташит, Описание, Даташиты
TM
Data Sheet
HI-5042 thru HI-5051
April 2000 File Number 3127.4
CMOS Analog Switches
This family of CMOS analog switches offers low resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
operating signal voltage and current. rON remains
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
0oC and 75oC. rON is nominally 25for HI-5049 and
HI-5051 and 50for HI-5042 through HI-5047.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at 25oC).
This family of switches also features very low power
operation (1.5mW at 25oC).
There are 7 devices in this switch series which are
differentiated by type of switch action and value of rON (see
Functional Description Table). The HI-504X and HI-505X
series switches can directly replace IH-5040 series devices,
and are functionally compatible with the DG180 and DG190
family.
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE
HI1-5042-2
HI1-5043-2
HI1-5043-5
HI3-5043-5
HI9P5043-5
HI1-5047-5
HI1-5049-5
HI1-5051-2
HI1-5051-5
-55 to 125
-55 to 125
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
-55 to 125
0 to 75
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
HI3-5051-5
HI9P5051-9
0 to 75
-40 to 85
16 Ld PDIP
16 Ld SOIC
PKG. NO.
F16.3
F16.3
F16.3
E16.3
M16.15
F16.3
F16.3
F16.3
F16.3
E16.3
M16.15
Features
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . ±15V
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 25
• High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA
• Break-Before-Make Switching
- Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns
- Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns
• No Latch-Up
• Input MOS Gates are Protected from Electrostatic
Discharge
• DTL, TTL, CMOS, PMOS Compatible
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
S
A NP
D
Functional Description
PART NUMBER
HI-5042
HI-5043
HI-5047
HI-5049
HI-5051
TYPE
SPDT
Dual SPDT
4PST
Dual DPST
Dual SPDT
rON
50
50
50
25
25
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000









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HI-5042 Даташит, Описание, Даташиты
HI-5042 thru HI-5051
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
SPDT
HI-5042 (50)
4PST
HI-5047 (50)
D1 1
2
D2 3
S2 4
5
6
7
8
16 S1
15 A
14 V-
13 VR
12 VL
11 V+
10
9
D2 1
2
D1 3
S1 4
S4 5
D4 6
7
D3 8
16 S2
15 A
14 V-
13 VR
12 VL
11 V+
10
9 S3
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Dual Control
DUAL SPDT
HI-5043 (50), HI-5051 (25)
DUAL DPST
HI-5049 (25)
D1 1
2
D3 3
S3 4
S4 5
D4 6
7
D2 8
16 S1
15 A1
14 V-
13 VR
12 VL
11 V+
10 A2
9 S2
D1 1
2
D3 3
S3 4
S4 5
D4 6
7
D2 8
16 S1
15 A1
14 V-
13 VR
12 VL
11 V+
10 A2
9 S2
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Switch Functions (SWITCHES SHOWN FOR LOGIC “1” INPUT)
SPDT
HI-5042 (50)
DUAL SPDT
HI-5043 (50)
16
S1
VL
12
V+
11
1
D1
4
S2
3
D2
15
A
13
VR
14
V-
S1
16
4
S3
A1
15
A2
S2
10
9
5
S4
VL
12
V+
11
1
3
D1
D3
13
VR
8
6
14
V-
D2
D4
4PST
HI-5047 (50)
S1 4
S2 16
9
S3
S4 5
A 15
VL
12
V+
11
3
1
8
6
D1
D2
D3
D4
13
VR
14
V-
DUAL DPST
HI-5049 (25)
16
S1 4
S3 15
A1
10
A2
S2
9
5
S4
VL
12
V+
11
1
3
D1
D3
13
VR
8
6
14
V-
D2
D4
DUAL SPDT
HI-5051 (25)
16
S1 4
S3 15
A1
10
A2
S2
9
5
S4
VL
12
V+
11
1
3
D1
D3
13
VR
8
6
14
V-
D2
D4
2









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HI-5042 Даташит, Описание, Даташиты
Schematic Diagrams
VL
QP3
HI-5042 thru HI-5051
R6
QP4
P15
P14
R3
N13
P16
QP1
QN1
V+
QP5
QP6
R4
QP8
R5
R2
QP7
VR
P13
V+
QN2
QP2
R7
N14 N15
N16
TO VR
V-
to VL
NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits.
TTL/CMOS REFERENCE CIRCUIT (NOTE)
A1 (A2)
V+
IN
P2
N1
N3
N2
V-
P1
OUT
A1 (A2)
P3
SWITCH CELL
V+
V+
R4
A
200
D1
D2
V-
P1
N1
VR'
VL'
P2
N2
P5
P4
P6 P7
N6 N7
N4
N5
P8 P9
N8 N9
N3
V-
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
P10
N10
P11
N11
P12
A1
A1
A2
A2
N12
3










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