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PDF HI-509 Data sheet ( Hoja de datos )

Número de pieza HI-509
Descripción Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! HI-509 Hoja de datos, Descripción, Manual

Data Sheet
HI-506, HI-507, HI-508, HI-509
June 1999 File Number 3142.2
Single 16 and 8/Differential 8-Channel and
4-Channel CMOS Analog Multiplexers
The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS
multiplexers each include an array of sixteen and eight
analog switches respectively, a digital decoder circuit for
channel selection, voltage reference for logic thresholds, and
an enable input for device selection when several
multiplexers are present. The Dielectric Isolation (DI)
process used in fabrication of these devices eliminates the
problem of latchup. DI also offers much lower substrate
leakage and parasitic capacitance than conventional
junction isolated CMOS (see Application Notes AN520 and
AN521).
The switching threshold for each digital input is established by
an internal +5V reference, providing a guaranteed minimum
2.4V for logic “1” and maximum 0.8V for logic “0”. This allows
direct interface without pullup resistors to signals from most
logic families: CMOS, TTL, DTL and some PMOS. For
protection against transient overvoltage, the digital inputs
include a series 200resistor and diode clamp to each
supply.
The HI-506 is a single 16-Channel, the HI-507 is an
8-Channel differential, the HI-508 is a single 8-Channel and
the HI-509 is a 4-Channel differential multiplexer.
If input overvoltages are present, the HI-546/HI-547/HI-548/
HI-549 multiplexers are recommended.
Features
• Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 180
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . ±15V
• TTL/CMOS Compatible
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . .44V
• Break-Before-Make Switching
• No Latch-Up
• Replaces DG506A/DG506AA and DG507A/DG507AA
• Replaces DG508A/DG508AA and DG509A/DG509AA
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Ordering Information
PART NUMBER
HI9P0506-9
HI3-0506-5
HI4P0506-5
HI1-0506-5
TEMP.
RANGE (oC)
PACKAGE
-40 to 85 28 Ld SOIC
0 to 75 28 Ld PDIP
0 to 75 28 Ld PLCC
0 to 75 28 Ld CERDIP
HI1-0506-4
HI1-0506-2
HI4P0507-5
HI3-0507-5
HI1-0507-2
-25 to 85
-55 to 125
0 to 75
0 to 75
-55 to 125
28 Ld CERDIP
28 Ld CERDIP
28 Ld PLCC
28 Ld PDIP
28 Ld CERDIP
HI1-0508-5
HI3-0508-5
HI1-0508-4
HI1-0508-2
HI4P0508-5
HI9P0508-9
HI9P0508-5
0 to 75
0 to 75
-25 to 85
-55 to 125
0 to 75
-40 to 85
0 to 75
16 Ld CERDIP
16 Ld PDIP
16 Ld CERDIP
16 Ld CERDIP
20 Ld PLCC
16 Ld SOIC
16 Ld SOIC
HI9P0509-5
HI1-0509-4
HI1-0509-5
HI3-0509-5
HI4P0509-5
0 to 75
-25 to 85
0 to 75
0 to 75
0 to 75
16 Ld SOIC
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
20 Ld PLCC
HI1-0509-2
-55 to 125 16 Ld CERDIP
PKG.
NO.
M28.3
E28.6
N28.45
F28.6
F28.6
F28.6
N28.45
E28.6
F28.6
F16.3
E16.3
F16.3
F16.3
N20.35
M16.15
M16.15
M16.15
F16.3
F16.3
E16.3
N20.35
F16.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




HI-509 pdf
HI-506, HI-507, HI-508, HI-509
Functional Diagrams
HI-506
HI-507
IN 1
IN 2
IN 16
DECODER/
DRIVER
OUT
5V
REF
LEVEL
SHIFT
DIGITAL
INPUT
†† ††
PROTECTION
A0 A1 A2 A3 EN
IN 1A
IN 8A
IN 1B
IN 8B
DECODER/
DRIVER
OUT A
OUT B
5V
REF
LEVEL
SHIFT
DIGITAL
INPUT
††††
PROTECTION
A0 A1 A2 EN
HI-508
IN 1 OUT
IN 2
DECODER/
DRIVER
IN 8
5V
REF
LEVEL
SHIFT
DIGITAL
INPUT
††††
PROTECTION
A0 A1 A2 EN
IN 1A
IN 4A
IN 1B
IN 4B
HI-509
DECODER/
DRIVER
OUT A
OUT B
5V
REF
DIGITAL
INPUT
PROTECTION
LEVEL
SHIFT
††
A0 A1
EN
5

5 Page





HI-509 arduino
HI-506, HI-507, HI-508, HI-509
Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified (Continued)
+15V
600
400
200
0
2 3 4 5 13 14 15
LOGIC LEVEL (HIGH) (V)
FIGURE 5A. ACCESS TIME vs LOGIC LEVEL (HIGH)
VA 50
3.5V
V+
A3 IN 1
A2
IN 2 THRU
IN 7/15
A1 HI-506
A0 IN 16
EN
GND
OUT
V-
±10V
+10V
10
k
-15V
Similar connection for HI-507/HI-508/
HI-509
FIGURE 5B. TEST CIRCUIT
50
pF
50%
3.5V ADDRESS
DRIVE (VA)
0V
VA INPUT
2V/DIV.
S1 ON
+10V
OUTPUT
10%
-10V
tA
FIGURE 5C. MEASUREMENT POINTS
FIGURE 5. ACCESS TIME
OUTPUT
5V/DIV.
S16 ON
200ns/DIV.
FIGURE 5D. WAVEFORMS
+15V
VA 50
3.5V
A3 V+
HI-506
A2 IN 1
IN 2 THRU
IN 7/IN 15
A1 IN 8 /16
A0
EN
GND
OUT
V-
200
-15V
Similar connection for HI-507/HI-508/HI-509
FIGURE 6A. TEST CIRCUIT
+5V
VOUT
50pF
11

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