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HI-6010CT PDF даташит

Спецификация HI-6010CT изготовлена ​​​​«Holt Integrated Circuits» и имеет функцию, называемую «ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS».

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Номер произв HI-6010CT
Описание ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS
Производители Holt Integrated Circuits
логотип Holt Integrated Circuits логотип 

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HI-6010CT Даташит, Описание, Даташиты
HI-6010
GENERAL DESCRIPTION
The HI-6010 is a CMOS integrated circuit designed to
interface the avionics data bus standard ARINC 429 to an
8 bit port. It contains one receiver and one transmitter.
They operate independently except for the self test option
and the parity option. The receiver demands that the
incoming data meet the standard protocol and the
transmitter outputs a standard protocol stream.
The HI-6010 provides flexible options for interfacing to the
user system. The controlling processor can operate both
the receiver and transmitter either by using hard wired
flags and gates at the pins or by using software reads and
writes of the Status Register and Control Register or a
combination thereof.
The chip is programmable to operate with single 8 bit
bytes requiring "on the fly transmitter loading and receiver
downloading" or to operate in 32 bit "extended buffer"
mode. In addition there is an option to use automatic label
recognition after loading 8 possible labels for comparison.
Parity and self test are also software programmable.
Master Reset is activated only by taking theMRpinhigh.
Two clock inputs allow independent selection of the data
rates of the transmitter and receiver. Each must be 4X the
desired ARINC 429 frequency.
Error flags are generated for transmitter underwrites and
for receiver data framing miscues, parity errors, and buffer
overwrites.
The HI-6010 is a 5 volt chip that will require data transla-
tion from and to the ARINC bus. The HI-8482 and HI-8588
line receivers are available for the receiver side and the
HI-318X, HI-838X and HI-858X line drivers are available
for the transmitter side. The HI-8590 is also available with
a line driver and a line receiver in a single 16-pin thermally
enhanced ESOIC package.
FEATURES
! ARINC 429 protocol controller with interface to
an 8 bit bus
! Automatic label recognition option
! 8 bit or 32 bit buffering option
! Self test and parity options
! CMOS / TTL logic pins
! Plastic and ceramic package options - surface
mount or DIP
! Military processing available
PIN CONFIGURATION (Top View)
VSS 1
WEF 2
CTS 3
TXC 4
HFS 5
MR 6
TXE 7
RXRDY 8
TXRDY 9
TXD0 10
TXD1 11
RXC 12
FCR 13
RXD0 14
28 RE
27 C/D
26 CS
25 WE
24 D7
23 D6
22 D5
21 D4
20 D3
19 D2
18 D1
17 D0
16 RXD1
15 VDD
Pin numbers apply for plastic and ceramic DIP and
for plastic PLCC. Consult factory for pin out of 48
lead ceramic leadless chip carrier.
! Avionics Data Communication
! Serial to Parallel Conversion
! Parallel to Serial Conversion
! VDD = 5.0 VOLTS ±5%
! VSS = 0.0 VOLTS
(DS6010 Rev. A)
HOLT INTEGRATED CIRCUITS
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HI-6010CT Даташит, Описание, Даташиты
HI-6010
PIN SYMBOL FUNCTION
1 VSS
2 WEF
3 CTS
4 TXC
5 HFS
6 MR
7 TXE
8 RXRDY
9 TXRDY
10 TXD0
11 TXD1
12 RXC
13 FCR
14 RXD0
15 VDD
16 RXD1
17 D0
18 D1
19 D2
20 D3
21 D4
22 D5
23 D6
24 D7
25 WE
26 CS
27 C/D
28 RE
POWER
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
POWER
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
DESCRIPTION
0.0 Volts
Error indication if high. Status register must be read to determine specific error.
Enables data transmission when low.
Source clock for data transmission. 4 times bit rate.
Hardware feature select.
Master reset, active high.
Low when transmission in progress.
High when data of received word is available.
High when data of a transmitted word may be input.
"Zeroes" data output of transmitter.
"Ones" data output of transmitter.
Source clock for data reception. 4 times bit rate.
First character received flag.
"Zeroes" data input to receiver.
5 Volts ±5%
"Ones" data input to receiver.
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
8 bit data bus input control active low.
Chip select, active low.
High for control or status register operations, low for data
8 bit data bus output control, active low.
The receiver logic is independent of the transmitter except in
the following ways:
1. Self Test
2. Parity Option
goes high for any one of three receiver errors. The status
register will show which of the three errors occurred:
Status Register Bit
Error
SR3
Received a parity error
SR4
Data Overwritten
SR5
Receiving sequence error
In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
external receiver clock is replaced with the transmitter clock.
The parity option affects both the receiver and transmitter.
Either both are operational or neither.
HARDWARE CONTROL OF THE RECEIVER
PIN 2 - WEF
WEF is an error indicator. It goes high for a transmitter
"underwrite" (failure to keep up with byte loading) and pin 2
The possible Receiver sequence errors are:
1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.
There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
Errors are cleared by MR or by reading the Status Register.
PIN 5 - HFS and the CONTROL REGISTER
This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip. If HFS is low, the
HOLT INTEGRATED CIRCUITS
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HI-6010CT Даташит, Описание, Даташиты
HI-6010
PIN 14 - RXD0 and PIN 16 - RXD1
receiver is not programmable to the 32 bit "extended buffer"
mode nor to the label recognition mode. Affecting the
receiver:
CONTROL PROGRAM PIN 5
BIT NAME VALUE VALUE
OPERATION
CR1 X 0 No action
0 1 No action
1 1 Next 8 data read cycles will read
stored labels. One time only sequence
on each transiton of CR1 to a 1.
CR2 0 X Receiver is disabled
1 X Receiver is enabled
CR3* 0 X RXRDY goes high normally
1 X Blocks RXRDY for one ARINC word
CR4 0 X Self test disabled
1 X Self test enabled
CR5 0 0 No parity errors enabled and 32nd
bit is data
1 0 Parity error flag enabled
0 1 32 bit "extended mode" enabled and
parity enabled.
1 1 8 bit "one byte at a time" mode and
parity enabled.
CR7 X 0 Label recognition not programmable
0 1 Label recognition disabled
1 1 Label recognition enabled
* CR3 will be automatically reset to 0 after being programmed
to a 1 at the completion of an ARINC word reception. This
allows a software label recognition different from the automatic
option available.
These pins must be 5 volt logic levels. There must be a
translator between the ARINC bus and these inputs.
Typically a receiver chip, such as the HI-8482 or HI-8588
is inserted between the ARINC bus and the logic chips.
RXD0 is looking for a high level for zero inputs and RXD1 is
looking for a high level for one inputs. When both inputs are
low this is referred to as the Null state.
SOFTWARE CONTROL OF THE RECEIVER
By writing to the Control Register and reading the Status
Register the controlling processor can operate the receiver
without hardware interrupts. The Control Register in
combination with the wiring of pin 5 was explained above.
The Status Register bits pertaining to the receiver are
explained below:
STATUS BIT VALUE
MEANING
SR1 0 No receiver data
1 Receiver data ready
SR3
0 No parity error
1 Parity error - Parity was even
SR4
0 Receiver data not overwritten
1 Receiver data was overwritten
SR5
0 Receiver data received without framing error
1 Framing error - Did not receive exactly 32
good bits
SR6
0 Did not receive first byte
1 Received first byte - Same flag as pin 13
COMMUNICATING WITH THE CONTROL AND
STATUS REGISTERS
PIN 6 - MR
When MR is a 1, the control word is set to 0X10 0101 (CR7 -
CR0). For the receiver this sets up 8 bit mode with the
receiver and parity enabled. MR also initializes the registers
and logic. The first ARINC reception will only occur after a
word gap.
PIN 8 - RXRDY
In 8 bit mode, this pin goes high whenever 8 bits are received
without error. In 32 bit mode this pin goes high after all 32 bits
are received with no error. This flag may be inhibited for one
ARINC word if CR3 is programmed to 1. This flag is also
inhibited in label recognition if the incoming ARINC label does
notmatch one of the stored 8 labels.
PIN 12 - RXC
This pin must have a clock applied that is 4X the desired
receive frequency.
PIN 13 - FCR
In 8 bit mode, this pin flags the first character (byte) received.
In 32 bit mode, this pin goes high for a valid 32 bit word. The
pin is not affected by CR3 programming.
Pin 27, C/D, must be high to read the status register or write
the control register. Reading the status register resets
errors. There is no provision to read the control register.
LABEL RECOGNITION OPTION
Pin 5 must be high if label recognition is selected in either the
8 or 32 bit modes and all eight label buffers must be written
using redundant labels, if necessary.
The chip compares the incoming label to the stored labels. If
a match is found, the data is processed. If a match is not
found, no indicators of receiving ARINC data are presented.
LOADING LABELS
After the write that changes CR7 from 0 to 1, the next 8 writes
of data (C/D is a zero for data) will load the label registers.
Labels must be loaded whenever pin 5 goes from low to
high.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 8 data
reads are labels.
HOLT INTEGRATED CIRCUITS
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