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HI-8281PJT PDF даташит

Спецификация HI-8281PJT изготовлена ​​​​«Holt Integrated Circuits» и имеет функцию, называемую «ARINC 429 LINE DRIVER AND DUAL RECEICER».

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Номер произв HI-8281PJT
Описание ARINC 429 LINE DRIVER AND DUAL RECEICER
Производители Holt Integrated Circuits
логотип Holt Integrated Circuits логотип 

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HI-8281PJT Даташит, Описание, Даташиты
HI-8281
January 2001
GENERAL DESCRIPTION
The HI-8281 device from Holt Integrated Circuits is a silicon
gate CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. The device provides
two receivers, an independent transmitter and line driver
capability in a single package. The receiver input circuitry
and logic are designed to meet the ARINC 429
specifications for loading, level detection, timing, and
protocol. The transmitter section provides the ARINC 429
communication protocol and the line driver circuits provide
the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8281 examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
FEATURES
! ARINC specification 429 compatible
! Direct receiver and transmitter interface to
ARINC bus in a single device.
! 16-Bit parallel data bus.
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
! Parity functions
! Low power
! Industrial & full military temperature ranges
PIN CONFIGURATION (Top View)
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
(See page 4-27 for additional pin configuration)
(DS8281 Rev. A)
HOLT INTEGRATED CIRCUITS
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HI-8281PJT Даташит, Описание, Даташиты
HI-8281
SIGNAL
VCC
V+
V-
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
TX/R
FUNCTION
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
OUTPUT
PL1
PL2
TXA(OUT)
TXB(OUT)
ENTX
CWSTR
CLK
TX CLK
MR
SLP1.5
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
DESCRIPTION
+5V ±5%
+12V ± 5% or +15V ± 10%
-12V ± 5% or -15V ± 10%
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0 V - both pins must be connected
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
After transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Line driver output - A side
Line driver output - B side
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
Logic input to control the slope of the differential output signal. HIGH = 1.5 µs
HOLT INTEGRATED CIRCUITS
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HI-8281PJT Даташит, Описание, Даташиты
HI-8281
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8282 contains 10 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS FUNCTION CONTROL
PIN
DESCRIPTION
BDO5
If enabled, an internal connection
SELF TEST 0 = ENABLE is made passing 429DO and
429DO to the receiver logic inputs
RECEIVER 1
BDO6 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
If Receiver 1 Decoder is
- enabled, the ARINC bit 9
must match this bit
BDO8
-
If Receiver 1 Decoder is
- enabled, the ARINC bit 10
must match this bit
RECEIVER 2
BDO9 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BD10
-
If Receiver 2 Decoder is
- enabled, then ARINC bit 9
must match this bit
BD11
-
If Receiver 2 Decoder is
- enabled, then ARINC bit 10
must match this bit
BD12
INVERT
XMTR
PARITY
Logic 0 enables normal odd parity
1 = ENABLE and Logic 1 enables even parity
output in transmitter 32nd bit
BD13 XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14 RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
BIT
BYTE 2
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BIT
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8282 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
HOLT INTEGRATED CIRCUITS
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