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PDF HEF4013B Data sheet ( Hoja de datos )
| Número de pieza | HEF4013B | |
| Descripción | Dual D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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HEF4013B
Dual D-type flip-flop
Rev. 8 — 21 November 2011
Product data sheet
1. General description
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD),
clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is
LOW and is transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs.
The outputs are buffered for best system performance. The clock input’s Schmitt-trigger
action makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Counters and dividers
Registers
Toggle flip-flops
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number
Package
Name
Description
HEF4013BP
DIP14
plastic dual in-line package; 14 leads (300 mil)
HEF4013BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
HEF4013BTT
TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT402-1
1 page  
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
10. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions VDD
Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit
Min Max Min Max Min Max Min Max
VIH
HIGH-level
IO < 1 A
5 V 3.5 - 3.5 - 3.5 - 3.5
-V
input voltage
10 V
7.0 - 7.0 - 7.0 -
7.0
-V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level IO < 1 A
5V
input voltage
10 V
- 1.5 - 1.5 - 1.5 - 1.5 V
- 3.0 - 3.0 - 3.0 - 3.0 V
15 V
- 4.0 - 4.0 - 4.0 - 4.0 V
VOH HIGH-level IO < 1 A
5 V 4.95 - 4.95 - 4.95 - 4.95 - V
output voltage
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level IO < 1 A
5V
output voltage
10 V
- 0.05 - 0.05 - 0.05 - 0.05 V
- 0.05 - 0.05 - 0.05 - 0.05 V
15 V
- 0.05 - 0.05 - 0.05 - 0.05 V
IOH
HIGH-level
VO = 2.5 V
5V
output current VO = 4.6 V
5V
- 1.7 - 1.4 - 1.1 - 1.1 mA
- 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V
10 V
- 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15 V
- 4.2 - 3.4 - 2.4 - 2.4 mA
IOL
LOW-level
VO = 0.4 V
5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
output current VO = 0.5 V
10 V
1.6
-
1.3
-
0.9
-
0.9
- mA
VO = 1.5 V
15 V
4.2
-
3.4
-
2.4
-
2.4
- mA
II input leakage
current
15 V
- 0.1 - 0.1 - 1.0 - 1.0 A
IDD supply current all valid input 5 V
combinations; 10 V
IO = 0 A
15 V
- 1.0 - 1.0 - 30 - 30 A
- 2.0 - 2.0 - 60 - 60 A
- 4.0 - 4.0 - 120 - 120 A
CI input
capacitance
- - - - 7.5 - - - - pF
HEF4013B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
5 of 16
5 Page 
NXP Semiconductors
SO14: plastic small outline package; 14 leads; body width 3.9 mm
HEF4013B
Dual D-type flip-flop
SOT108-1
y
Z
14
D
pin 1 index
1
e
EA
X
c
HE
vM A
8
A2
A1
7
bp
wM
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E(1) e
HE
L
Lp
Q
v
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.244
0.228
0.041
0.039
0.016
0.028
0.024
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT108-1
IEC
076E06
REFERENCES
JEDEC
JEITA
MS-012
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 11. Package outline SOT108-1 (SO14)
HEF4013B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
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