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HEF4028B PDF даташит

Спецификация HEF4028B изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «BCD to decimal decoder».

Детали детали

Номер произв HEF4028B
Описание BCD to decimal decoder
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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HEF4028B Даташит, Описание, Даташиты
HEF4028B
BCD to decimal decoder
Rev. 8 — 17 November 2011
Product data sheet
1. General description
The HEF4028B is a 4-bit BCD to decimal decoder, a 4-bit BCO to octal decoder with
active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer. The outputs are fully
buffered for best performance.
When used as a BCD to decimal decoder a 1-2-4-8 BCD code applied to inputs A0 to A3
causes the selected output to be HIGH. The other nine outputs will be LOW.
To use the HEF4028B as a BCO to octal decoder, input A3 is an active LOW enable pin
and outputs Y8 and Y9 are not used. A 1-2-4 BCO code applied to inputs A0 to A2 causes
the selected output (Y0 to Y7) to be HIGH. The other seven outputs will be LOW. When
A3 is HIGH outputs (Y0 to Y7) will be forced LOW.
When used as an 8-output (Y0 to Y7) inverting demultiplexer A0 to A2 are used as
address inputs and A3 is the data input. Outputs Y8 and Y9 are not used.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name Description
HEF4028BP DIP16 plastic dual in-line package; 16 leads (300 mil)
HEF4028BT SO16 plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1









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HEF4028B Даташит, Описание, Даташиты
NXP Semiconductors
4. Functional diagram
HEF4028B
BCD to decimal decoder
Fig 1. Functional diagram
A0 A1 A2 A3
10 13 12 11
DECODER
3 14 2 15 1 6 7 4 9 5
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
001aae598
A0
A1
A2
A3
Fig 2. Logic diagram
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
001aae600
HEF4028B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
2 of 13









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HEF4028B Даташит, Описание, Даташиты
NXP Semiconductors
HEF4028B
BCD to decimal decoder
5. Pinning information
5.1 Pinning
Fig 3. Pin configuration
HEF4028B
Y4 1
Y2 2
Y0 3
Y7 4
Y9 5
Y5 6
Y6 7
VSS 8
16 VDD
15 Y3
14 Y1
13 A1
12 A2
11 A3
10 A0
9 Y8
001aae599
5.2 Pin description
Table 2.
Symbol
Y0 to Y9
VSS
A0 to A3
VDD
Pin description
Pin
3, 14, 2, 15, 1, 6, 7, 4, 9, 5
8
10, 13, 12, 11
16
6. Functional description
Description
output (active HIGH)
ground supply voltage
address input
supply voltage
Table 3. Function table [1]
Inputs
Outputs
A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
L L L LHL L L L L L L L L
L L L HL H L L L L L L L L
L L H LL L HL L L L L L L
L L H HL L L H L L L L L L
L H L LL L L L HL L L L L
L H L HL L L L L H L L L L
L H H LL L L L L L HL L L
L H H HL L L L L L L H L L
H L L LL L L L L L L L HL
HEF4028B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 13










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