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PDF HEF4046B Data sheet ( Hoja de datos )
| Número de pieza | HEF4046B | |
| Descripción | Phase-locked loop | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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HEF4046B
Phase-locked loop
Rev. 6 — 24 March 2016
Product data sheet
1. General description
The HEF4046B is a phase-locked loop circuit that consists of a linear Voltage Controlled
Oscillator (VCO) and two different phase comparators with a common signal input
amplifier and a common comparator input. A 7 V regulator (Zener) diode is provided for
supply voltage regulation if necessary. For a functional description see Section 6.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
Description
HEF4046BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
1 page  
NXP Semiconductors
HEF4046B
Phase-locked loop
Phase comparator 2 is an edge-controlled digital memory network. It consists of four
flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers with a
common output node. When the p-type or n-type drivers are ON, they pull the output up to
VDD or down to VSS respectively. This type of phase comparator only acts on the
positive-going edges of the signals at SIG_IN and COMP_IN. Therefore, the duty factors
of these signals are not of importance.
If the signal input frequency is higher than the comparator input frequency, the p-type
output driver is maintained ON most of the time, and both the n and p-type drivers are
OFF (3-state) the remainder of the time. If the signal input frequency is lower than the
comparator input frequency, the n-type output driver is maintained ON most of the time,
and both the n and p-type drivers are OFF the remainder of the time. If the signal input
and comparator input frequencies are equal, but the signal input lags the comparator input
in phase, the n-type output driver is maintained ON for a time corresponding to the phase
difference. If the comparator input lags the signal input in phase, the p-type output driver is
maintained ON for a time corresponding to the phase difference. Subsequently, the
voltage at the capacitor of the low-pass filter connected to this phase comparator is
adjusted until the signal and comparator inputs are equal in both phase and frequency. At
this stable point, both p and n-type drivers remain OFF and thus the phase comparator
output becomes an open circuit and keeps the voltage at the capacitor of the low-pass
filter constant.
Moreover, the signal at the phase comparator pulse output (PCP_OUT) is a HIGH level,
which can be used for indicating a locked condition. Thus, for phase comparator 2, no
phase difference exists between the signal and comparator inputs over the full VCO
frequency range. Moreover, the power dissipation due to the low-pass filter is reduced
when this type of phase comparator is used, because both p and n-type output drivers are
OFF for most of the signal input cycle. It should be noted that the PLL lock range for this
type of phase comparator is equal to the capture range, independent of the low-pass filter.
With no signal present at the signal input, the VCO is adjusted to its lowest frequency for
phase comparator 2. Figure 5 shows typical waveforms for a PLL employing this type of
locked phase comparator.
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Product data sheet
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Fig 5. Typical waveforms for phase-locked loop with a locked phase comparator 2
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 24 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
HEF4046B
Phase-locked loop
11.1 VCO component selection
Recommended range for R1 and R2: 10 k to 1 M; for C1: 50 pF to any practical value.
1. VCO without frequency offset (R2 = ).
a. Given f0: use f0 with Figure 7 to determine R1 and C1.
b. Given fmax: calculate f0 from f0 = 0.5fmax; use f0 with Figure 7 to determine R1 and
C1.
2. VCO with frequency offset.
a. Given f0 and 2fL : calculate fmin from the equation fmin = f0 2fL; use fmin with
Figure 8 to determine R2 and C1; calculate f--m----a---x from the equation
fmin
f--m----a---x = f--0----+-----2---f--L- ; use f--m----a---x with Figure 9 to determine the ratio R2/R1 to obtain
fmin f0 – 2fL
fmin
R1.
b. Given fmin and fmax: use fmin with Figure 8 to determine R2 and C1; calculate
f--m----a---x ;
fmin
use f--m----a---x with Figure 9 to determine R2/R1 to obtain R1.
fmin
IR
+]
DDH
& S)
Fig 7.
Tamb = 25 C; VCO_IN at 0.5VDD;
INH_IN at VSS; R2 = .
Lines (1), (4), and (7): VDD = 15 V;
Lines (2), (5), and (8): VDD = 10 V;
Lines (3), (6), and (9): VDD = 5 V;
Lines (1), (2), and (3): R1 = 10 k;
Lines (4), (5), and (6): R1 = 100 k;
Lines (7), (8), and (9): R1 = 1 M.
Typical center frequency as a function of
capacitor C1
IPLQ
+]
DDH
& S)
Tamb = 25 C; VCO_IN at VSS; INH_IN at VSS; R1 = .
Lines (1), (4), and (7): VDD = 15 V;
Lines (2), (5), and (8): VDD = 10 V;
Lines (3), (6), and (9): VDD = 5 V;
Lines (1), (2), and (3): R2 = 10 k;
Lines (4), (5), and (6): R2 = 100 k;
Lines (7), (8), and (9): R2 = 1 M.
Fig 8. Typical frequency offset as a function of
capacitor C1
HEF4046B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 24 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 19
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet HEF4046B.PDF ] | |
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