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HEF4050B PDF даташит

Спецификация HEF4050B изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «HEX non-inverting buffers».

Детали детали

Номер произв HEF4050B
Описание HEX non-inverting buffers
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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HEF4050B Даташит, Описание, Даташиты
HEF4050B
Hex non-inverting buffers
Rev. 8 — 18 November 2011
Product data sheet
1. General description
The HEF4050B provides six non-inverting buffers with high current output capability
suitable for driving TTL or high capacitive loads. Since input voltages in excess of the
buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels
of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic
elements is shown in Table 3.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Accepts input voltages in excess of the supply voltage
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
LOCMOS (Local Oxidation CMOS) to DTL/TTL converter
HIGH sink current for driving two TTL loads
HIGH-to-LOW level logic conversion
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name
Description
HEF4050BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4050BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1









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HEF4050B Даташит, Описание, Даташиты
NXP Semiconductors
5. Functional diagram
HEF4050B
Hex non-inverting buffers
3 1A
1Y 2
2A
5
2Y
4
7 3A
3Y 6
4A
9
4Y
10
5A
11
5Y
12
14 6A
6Y 15
001aae605
Fig 1. Logic symbol
input
1A 1Y
001aae607
VSS
001aae604
Fig 2. Logic diagram for one gate Fig 3. Input protection circuit
6. Pinning information
6.1 Pinning
Fig 4. Pin configuration
HEF4050B
VDD 1
1Y 2
1A 3
2Y 4
2A 5
3Y 6
3A 7
VSS 8
16 n.c.
15 6Y
14 6A
13 n.c.
12 5Y
11 5A
10 4Y
9 4A
001aae606
6.2 Pin description
Table 2.
Symbol
VDD
1Y to 6Y
Pin description
Pin
1
2, 4, 6, 10, 12, 15
Description
supply voltage
output
HEF4050B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
2 of 12









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HEF4050B Даташит, Описание, Даташиты
NXP Semiconductors
HEF4050B
Hex non-inverting buffers
Table 2.
Symbol
1A to 6A
VSS
n.c.
Pin description …continued
Pin
3, 5, 7, 9, 11, 14,
8
13, 16
7. Functional description
Description
input
ground supply voltage
not connected
Table 3. Guaranteed fan-out
Driven element
Standard TTL
74 LS
74 L
8. Limiting values
Guaranteed fan-out
2
9
16
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb 40 C to +85 C
DIP16 package
SO16 package
P power dissipation
per output
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Min
0.5
-
0.5
-
-
-
65
40
[1] -
[2] -
-
Max
+18
10
VDD + 0.5
10
10
50
+150
+85
Unit
V
mA
V
mA
mA
mA
C
C
750 mW
500 mW
100 mW
Table 5.
Symbol
VDD
VI
Tamb
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
Min Max
3 15
0 VDD
40 +85
Unit
V
V
C
HEF4050B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 12










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HEF4050BHEX non-inverting buffersNXP Semiconductors
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HEF4050BHEX non-inverting buffersPhilips
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