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HEF4093B PDF даташит

Спецификация HEF4093B изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Quad 2-input NAND Schmitt trigger».

Детали детали

Номер произв HEF4093B
Описание Quad 2-input NAND Schmitt trigger
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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HEF4093B Даташит, Описание, Даташиты
HEF4093B
Quad 2-input NAND Schmitt trigger
Rev. 9 — 15 December 2015
Product data sheet
1. General description
The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit.
The gate switches at different points for positive-going and negative-going signals. The
difference between the positive voltage (VT+) and the negative voltage (VT) is defined as
hysteresis voltage (VH).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Schmitt trigger input discrimination
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number
Package
Name
Description
HEF4093BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT108-1









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HEF4093B Даташит, Описание, Даташиты
NXP Semiconductors
5. Functional diagram
HEF4093B
Quad 2-input NAND Schmitt trigger
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Fig 1. Functional diagram
6. Pinning information
6.1 Pinning
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Fig 2. Logic diagram (one gate)
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Fig 3. Pin configuration
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HEF4093B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 14









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HEF4093B Даташит, Описание, Даташиты
NXP Semiconductors
HEF4093B
Quad 2-input NAND Schmitt trigger
6.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
VDD
VSS
Pin description
Pin
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
14
7
7. Functional description
Description
input
input
output
supply voltage
ground (0 V)
Table 3.
Input
nA
L
L
H
H
Function table[1]
nB
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Output
nY
H
H
H
L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min Max Unit
VDD supply voltage
IIK input clamping current
VI input voltage
IOK output clamping current
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
0.5 +18 V
- 10 mA
0.5 VDD + 0.5 V
- 10 mA
II/O input/output current
- 10 mA
IDD
Tstg
Tamb
Ptot
supply current
storage temperature
ambient temperature
total power dissipation
Tamb = 40 C to +125 C
SO14
-
65
40
[1] -
50
+150
+125
mA
C
C
500 mW
P power dissipation
per output
- 100 mW
[1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
HEF4093B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 14










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