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PDF HEF4094B Data sheet ( Hoja de datos )
| Número de pieza | HEF4094B | |
| Descripción | 8-stage shift-and-store register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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HEF4094B
8-stage shift-and-store register
Rev. 12 — 25 March 2016
Product data sheet
1. General description
The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input to parallel buffered 3-state outputs
QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive-going clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B
devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
HEF4094B devices when the clock has a slow rise time.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C.
Type number
Package
Name
Description
HEF4094BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
HEF4094BTS
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm
HEF4094BTT
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
1 page  
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min Max Unit
VDD supply voltage
IIK input clamping current
VI input voltage
IOK output clamping current
II/O input/output current
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
0.5 +18 V
- 10 mA
0.5 VDD + 0.5 V
- 10 mA
- 10 mA
IDD
Tstg
Tamb
Ptot
supply current
storage temperature
ambient temperature
total power dissipation
SO16, SSOP16 and TSSOP16
-
65
40
[1] -
50
+150
+125
500
mA
C
C
mW
P power dissipation
per output
- 100 mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VDD
VI
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
input transition rise and fall rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Typ Max Unit
3 - 15 V
0 - VDD V
40 - +125 C
- - 3.75 s/V
- - 0.5 s/V
- - 0.08 s/V
HEF4094B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 25 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
a. Input waveform
9,
QHJDWLYH
SXOVH
9
9,
SRVLWLYH
SXOVH
9
90
WI
WU
90
W:
90
WU
WI
90
W: DDM
9,
*
9''
'87
9(;7
92 5/
57 &/
DDM
b. Test circuit
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit
Table 10. Test data
Supply voltage Input
VDD
5 V to 15 V
VI
VSS or VDD
tr, tf
20 ns
VEXT
tPHL, tPLH
open
tPHZ, tPZH
VSS
tPLZ, tPZL
VDD
Load
CL
50 pF
RL
1 k
HEF4094B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 25 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 19
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