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PDF HD64F5388 Data sheet ( Hoja de datos )
| Número de pieza | HD64F5388 | |
| Descripción | Hardware Manual | |
| Fabricantes | Hitachi | |
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OMC942723001
H8/538F
HD64F5388
Hardware Manual
ADE-602-064
Free Datasheet http://www.nDatasheet.com
1 page  
4.3 Address Error ................................................................................................................. 78
4.3.1 Address Error in Instruction Prefetch ................................................................ 79
4.3.2 Address Error in Word Data Access .................................................................. 79
4.3.3 Address Error in Single-Chip Mode .................................................................. 80
4.4 Trace ............................................................................................................................ 81
4.5 Interrupts ........................................................................................................................ 82
4.6 Invalid Instructions ........................................................................................................ 83
4.7 Trap Instructions and Zero Divide ................................................................................. 83
4.8 Cases in which Exception Handling is Deferred ........................................................... 84
4.8.1 Instructions that Disable Exception Handling ................................................... 84
4.8.2 Disabling of Exceptions Immediately after a Reset .......................................... 85
4.8.3 Disabling of Interrupts after a Data Transfer Cycle .......................................... 85
4.9 Stack Status after Completion of Exception Handling .................................................. 86
4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions,
and Zero Divide Exceptions .............................................................................. 87
4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction .............. 87
4.10 Notes on Use of the Stack .............................................................................................. 87
Section 5 Interrupt Controller ...................................................................................... 89
5.1 Overview ........................................................................................................................ 89
5.1.1 Features .............................................................................................................. 89
5.1.2 Block Diagram ................................................................................................... 90
5.1.3 Register Configuration ....................................................................................... 91
5.2 Interrupt Sources ............................................................................................................ 92
5.2.1 NMI .................................................................................................................... 94
5.2.2 IRQ0 .................................................................................................................. 95
5.2.3 IRQ1 to IRQ3 .................................................................................................... 95
5.2.4 Internal Interrupts .............................................................................................. 98
5.3 Register Descriptions ..................................................................................................... 99
5.3.1 Interrupt Priority Registers A to F ..................................................................... 99
5.3.2 Timing of Priority Changes ............................................................................... 100
5.4 Interrupt Operations ....................................................................................................... 101
5.4.1 Operations up to Interrupt Acceptance .............................................................. 101
5.4.2 Interrupt Exception Handling ............................................................................ 103
5.4.3 Interrupt Exception Handling Sequence ............................................................ 105
5.4.4 Stack after Interrupt Exception Handling .......................................................... 107
5.5 Interrupts during DTC Operation .................................................................................. 108
5.6 Interrupt Response Time ................................................................................................ 109
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5 Page 
13.4.3 Analog Input Sampling and A/D Conversion Time .......................................... 422
13.4.4 External Triggering of A/D Conversion ............................................................ 424
13.4.5 Starting A/D Conversion by IPU ....................................................................... 424
13.5 Interrupts and DTC ........................................................................................................ 425
13.6 Usage Notes ................................................................................................................... 425
Section 14 Bus Controller ............................................................................................... 429
14.1 Overview ........................................................................................................................ 429
14.1.1 Features .............................................................................................................. 429
14.1.2 Block Diagram ................................................................................................... 430
14.1.3 Register Configuration ....................................................................................... 431
14.2 Register Descriptions ..................................................................................................... 431
14.2.1 Byte Area Top Register ..................................................................................... 431
14.2.2 Three-State Area Top Register .......................................................................... 432
14.2.3 Bus Control Register .......................................................................................... 433
14.3 Operation ....................................................................................................................... 436
14.3.1 Operation after Reset in Each Mode .................................................................. 436
14.3.2 Timing of Changes in Bus Areas and Bus Size ................................................. 441
14.3.3 I/O Port Expansion Function ............................................................................. 443
14.4 Usage Notes ................................................................................................................... 444
Section 15 RAM ................................................................................................................ 451
15.1 Overview ........................................................................................................................ 451
15.1.1 Block Diagram ................................................................................................... 451
15.1.2 Register Configuration ....................................................................................... 452
15.2 RAM Control Register ................................................................................................... 452
15.3 Operation ....................................................................................................................... 453
15.3.1 Expanded Modes (Modes 1 to 6) ....................................................................... 453
15.3.2 Single-Chip Mode (Mode 7) .............................................................................. 453
Section 16 Flash Memory ................................................................................................ 455
16.1 Overview......................................................................................................................... 455
16.1.1 Flash Memory Overview .................................................................................... 455
16.1.2 Mode Programming and Flash Memory Address Space .................................... 456
16.1.3 Features............................................................................................................... 456
16.1.4 Block Diagram.................................................................................................... 458
16.1.5 Input/Output Pins................................................................................................ 459
16.1.6 Register Configuration........................................................................................ 459
16.2 Register Descriptions...................................................................................................... 460
16.2.1 Flash Memory Control Register ......................................................................... 460
16.2.2 Erase Block Register 1........................................................................................ 462
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11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HD64F5388.PDF ] | |
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