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H5TQ1G63DFR-xxL PDF даташит

Спецификация H5TQ1G63DFR-xxL изготовлена ​​​​«Hynix» и имеет функцию, называемую «1Gb DDR3 SDRAM».

Детали детали

Номер произв H5TQ1G63DFR-xxL
Описание 1Gb DDR3 SDRAM
Производители Hynix
логотип Hynix логотип 

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H5TQ1G63DFR-xxL Даташит, Описание, Даташиты
1Gb DDR3 SDRAM
1Gb DDR3 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ1G83DFR-xxC
H5TQ1G83DFR-xxI
H5TQ1G83DFR-xxL
H5TQ1G83DFR-xxJ
H5TQ1G63DFR-xxC
H5TQ1G63DFR-xxI
H5TQ1G63DFR-xxL
H5TQ1G63DFR-xxJ
*Hynix Semiconductor reserves the right to change products or specifications without notice
Rev. 1.7 /Sep. 2011
1
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H5TQ1G63DFR-xxL Даташит, Описание, Даташиты
Revision History
Revision No.
History
1.0 Added IDD Value
1.1 Corrected Typo Error
1.2 Corrected Typo Error(Ordering Information)
1.3 Added 1866/2133 Speed Support
1.4 Added IDD Specification(1866/2133 Speed)
1.5 Modified OPERATING FREQUENCY Table
1.6 Added J and L-part support
1.7 Updated 1866/2133 x8 IDD Specification
and 1866 Frequency downbinning
Date
Aug. 2010
Sep. 2010
Oct. 2010
Dec. 2010
Dec. 2010
Dec. 2010
Jun. 2011
Sep. 2011
Remark
Rev. 1.7 /Sep. 2011
2
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H5TQ1G63DFR-xxL Даташит, Описание, Даташиты
Description
The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and
high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-
width.
Device Features and Ordering Information
FEATURES
• DQ Power & Power supply : VDD & VDDQ = 1.5V +/- • Programmable BL=4 supported (tCCD=2CLK) for Digi-
0.075V
tal consumer Applications.
• DQ Ground supply : VSSQ = Ground
• Programmable ZQ calibration supported
• Fully differential clock inputs (CK, CK) operation
• BL switch on the fly
• Differential Data Strobe (DQS, DQS)
• 8banks
• On chip DLL align DQ, DQS and DQS transition with CK • Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
transition
- 7.8 µs at -40oC ~ 85 oC
• DM masks write data-in at the both rising and falling
edges of the data strobe
- 3.9 µs at 85oC ~ 95 oC
Commercial Temperature ( 0oC ~ 85 oC)
• All addresses and control inputs except data,
Industrial Temperature ( -40oC ~ 85 oC)
data strobes and data masks latched on the
rising edges of the clock
• Auto Self Refresh supported
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 • JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
and 14 supported
• Driver strength selected by EMRS
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,
10
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• Programmable PASR(Partial Array Self-Refresh) for
Digital consumer Applications.
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• On Die Thermal Sensor supported
• 8 bit pre-fetch
* This product in compliance with the RoHS directive.
Rev. 1.7 /Sep. 2011
3
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