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PDF NPCT42x Data sheet ( Hoja de datos )
| Número de pieza | NPCT42x | |
| Descripción | Trusted Platform Module | |
| Fabricantes | nuvoTon | |
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NPCT42x Trusted Platform Module (TPM)
Preliminary
March 2011
Revision 1.1
General Description
The NPCT42x single-chip Trusted Platform Module (TPM) is
a family of third-generation, Nuvoton SafeKeeper technolo-
gy devices. The devices implement the Trusted Computing
Group (TCG) version 1.2 specifications for PC-Client TPM.
The NPCT42x devices are designed to reduce system boot
time and Trusted OS loading time. They provide a solution
for PC security for a wide range of PC applications.
The NPCT42x family of devices are Microsoft Windows
compliant and are supported by Linux kernel v2.6.18 and
higher.
Features
General
■ Single-chip TPM solution
— No external parts required
■ Compatible with TPM Main Specification Version 1.2
Revision 116 and PC Client Specific TPM Interface
Specification Version 1.21 Revision 72
■ Host Interface
— TPM 1.2 standard interface (TIS) with five localities
— Supports legacy locality by using TIS protocol with
I/O mapped registers
■ Secure General-Purpose I/O (GPIO)
— Five GPIO pins
— I/O pins individually configured as input or output
— Configurable internal pull-up resistors
— TCG 1.2-defined interface
— Dedicated Physical Presence (PP) pin with config-
urable pull-up or pull-down resistor
■ Tick Counter
Bus Interface
■ LPC Bus Interface
— Based on Intel’s LPC Interface Specification Revi-
sion 1.1, August 2002
— TPM 1.2 Interface (TIS)
Clocking and Supply
■ On-Chip Clock Generator
■ Power Supply
— 3.3V supply operation
— Separate pins for main (VDD) and standby (VSB)
power supplies
— Low standby power consumption
Software
■ TPM BIOS drivers: Memory Absent (MA) and Memory
Present (MP)
■ TPM Device Driver for Microsoft Windows
■ NTRU Cryptosystems (acquired by Security Innova-
tion) Core TCG Software Stack (CTSS)
■ Wave Systems Cryptographic Service Provider (CSP)
with either EMBASSY® Security Center (ESC) or
EMBASSY Trust Suite (ETS) OEM Edition
System Block Diagram
Chipset
Physical
Presence
NPCT42x
LPC Bus
SuperI/O
© 2011 Nuvoton Technology Corporation
GPIO
www.nuvoton.com
Free Datasheet http://www.Datasheet4U.com
1 page  
Table of Contents (Continued)
5.2.7 Notes and Exceptions .................................................................................................. 17
5.3 INTERNAL RESISTORS ........................................................................................................... 18
5.3.1 Pull-Up Resistor ........................................................................................................... 19
5.3.2 Pull-Down Resistor ...................................................................................................... 19
5.4 AC ELECTRICAL CHARACTERISTICS .................................................................................... 20
5.4.1 AC Test Conditions ................................................................................................... 20
5.4.2 Reset Timing ............................................................................................................... 21
Power-Up Reset ................................................................................................... 21
5.4.3 LPC Interface Timing ................................................................................................... 22
LCLK and LRESET ............................................................................................... 22
LPC Signals ............................................................................................................ 23
5.5 PACKAGE THERMAL INFORMATION ..................................................................................... 24
Physical Dimensions......................................................................................................................................... 25
Revision 1.1
5
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5 Page 
3.0 I/O Configuration Registers (Continued)
3.1.3 Reset Configuration Setup
The default configuration setup of the NPCT42x is:
● The configuration base address is according to Table 3 on page 10.
● TPM logical device is disabled.
● The TPM interface is in Legacy mode.
● All host configuration registers are set to their default values unless explicitly stated otherwise.
3.1.4 Register Type Abbreviations
The following abbreviations are used to indicate the Register Type:
● R/W= Read/Write.
● RO= Read-only.
Write 0 to reserved bits unless another “required value” is specified. This method can be used for registers containing bits
of all types.
Revision 1.1
11
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11 Page | ||
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