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PDF 74HC4053A Data sheet ( Hoja de datos )
| Número de pieza | 74HC4053A | |
| Descripción | (74HC4051A / 74HC4053A) Analog Multiplexers / Demultiplexers | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Analog Multiplexers/
Demultiplexers
High–Performance Silicon–Gate CMOS
MC54/74HC4051A
MC74HC4052A
MC54/74HC4053A
The MC54/74HC4051A, MC74HC4052A and MC54/74HC4053A utilize
silicon–gate CMOS technology to achieve fast propagation delays, low ON
resistances, and low OFF leakage currents. These analog multiplexers/
J SUFFIX
demultiplexers control analog voltages that may vary across the complete
power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout to the
16
1
CERAMIC PACKAGE
CASE 620–10
metal–gate MC14051AB, MC14052AB and MC14053AB. The Channel–Se-
lect inputs determine which one of the Analog Inputs/Outputs is to be
connected, by means of an analog switch, to the Common Output/Input.
When the Enable pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
For a multiplexer/demultiplexer with channel–select latches, see
16
1
DW SUFFIX
SOIC WIDE PACKAGE
CASE 751G–02
HC4351A.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADW
Ceramic
Plastic
SOIC
SOIC Wide
• Low Noise
MC74HCXXXXADT TSSOP
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
FUNCTION TABLE – MC54/74HC4051A
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
LOGIC DIAGRAM
Control Inputs
Enable
Select
CBA
ON Channels
MC54/74HC4051A
Single–Pole, 8–Position Plus Common Off
L LLL
L LLH
X0
X1
L LHL
X2
X0 13
X1 14
ANALOG
INPUTS/
OUTPUTS
X2 15
X3 12
X4 1
MULTIPLEXER/
DEMULTIPLEXER
X5 5
X6 2
X7 4
CHANNEL
SELECT
INPUTS
A 11
B 10
C9
ENABLE 6
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
3
X
COMMON
OUTPUT/
INPUT
L
L
L
L
L
H
Pinout: MC54/74HC4051A (Top View)
VCC X2 X1 X0 X3 A B C
16 15 14 13 12 11 10 9
12345678
X4 X6 X X7 X5 Enable VEE GND
L HH
HL L
HLH
HH L
HHH
XXX
X3
X4
X5
X6
X7
NONE
X = Don’t Care
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
10/97
© Motorola, Inc. 1997
1
REV 0
Free Datasheet http://www.Datasheet4U.com
1 page  
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V –55 to 25°C ≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
4.5
6.0
370
74
63
465 550 ns
93 110
79 94
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0 60
4.5 12
6.0 10
75 90 ns
15 18
13 15
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0 290
4.5 58
6.0 49
364 430 ns
73 86
62 73
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0 345
4.5 69
6.0 59
435 515 ns
87 103
74 87
Cin
CI/O
Maximum Input Capacitance, Channel–Select or Enable Inputs
Maximum Capacitance
Analog I/O
(All Switches Off)
Common O/I: HC4051A
HC4052A
HC4053A
10 10 10 pF
35 35 35 pF
130 130 130
80 80 80
50 50 50
Feedthrough
1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 13)*
HC4051A
HC4052A
HC4053A
45
80
45
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
Free Datasheet http://www.Datasheet4U.com
5 Page 
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
+5V
+5V
ANALOG
16
ANALOG
+5V
ON
–5V SIGNAL
SIGNAL
–5V
6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5V
8 9 DIGITAL SIGNALS
–5V
Figure 15. Application Example
VCC VCC VCC
Dx 16 Dx
ON/OFF
Dx Dx
VEE VEE
7
8
VEE
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
+5V
ANALOG
16
ANALOG
+5V
ON/OFF
VEE SIGNAL
SIGNAL
+5V
VEE
*
RRR
+5V
+5V
ANALOG
16
ANALOG
+5V
ON/OFF
VEE SIGNAL
SIGNAL
VEE
+5V
6 11
7 10
89
LSTTL/NMOS
CIRCUITRY
VEE * 2K ≤ R ≤ 10K
a. Using Pull–Up Resistors
6 11
7 10
89
VEE HCT
BUFFER
b. Using HCT Interface
LSTTL/NMOS
CIRCUITRY
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11
A
LEVEL
SHIFTER
13
X0
14
X1
10
B
LEVEL
SHIFTER
15
X2
12
X3
9
C
LEVEL
SHIFTER
1
X4
5
X5
6
ENABLE
LEVEL
SHIFTER
2
X6
4
X7
Figure 18. Function Diagram, HC4051A
3
X
High–Speed CMOS Logic Data
DL129 — Rev 6
11
MOTOROLA
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 74HC4053A.PDF ] | |
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