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PDF 7NK80Z Data sheet ( Hoja de datos )

Número de pieza 7NK80Z
Descripción STP7NK80Z
Fabricantes STMicroelectronics 
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No Preview Available ! 7NK80Z Hoja de datos, Descripción, Manual

STP7NK80Z - STP7NK80ZFP
STB7NK80Z - STB7NK80Z-1
N-channel 800V - 1.5- 5.2A - TO-220/TO-220FP/D2PAK/I2PAK
Zener-protected SuperMESH™ Power MOSFET
General features
Type
STP7NK80Z
STP7NK80ZFP
STB7NK80Z
STB7NK80Z-1
VDSS
(@Tjmax)
800V
800V
800V
800V
RDS(on)
< 1.8
< 1.8
< 1.8
< 1.8
ID
5.2A
5.2A
5.2A
5.2A
Extremely high dv/dt capability
100% avalange tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatibility
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage Power MOSFETs including revolutionary
MDmesh™ products.
Applications
Switching application
TO-220
3
2
1
TO-220FP
3
1
D2PAK
123
I2PAK
Internal schematic diagram
Order codes
Part number
STP7NK80Z
STP7NK80ZFP
STB7NK80ZT4
STB7NK80Z-1
Marking
P7NK80Z
P7NK80ZFP
B7NK80Z
B7NK80Z-1
Package
TO-220
TO-220FP
D²PAK
I²PAK
Packaging
Tube
Tube
Tape e reel
Tube
October 2006
Rev 5
1/18
www.st.com
18
Free Datasheet http://www.Datasheet4U.com

1 page




7NK80Z pdf
STP7NK80Z - STP7NK80ZFP - STB7NK80Z - STB7NK80Z-1
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4. On/off states
Symbol
Parameter
V(BR)DSS
Drain-source
Breakdown voltage
IDSS
Zero gate voltage
Drain Current (VGS = 0)
IGSS
Gate-body leakage
Current (VDS = 0)
VGS(th) Gate threshold voltage
RDS(on)
Static drain-source on
resistance
Test conditions
Min. Typ. Max. Unit
ID =1MA, VGS = 0
800
VDS = Max rating
VDS = Max rating, TC = 125°C
V
1 µA
50 µA
VGS = ± 20 V
VDS = VGS, ID = 100 µA
VGS = 10 V, ID = 2.6 A
± 10 µA
3 3.75 4.5
1.5 1.8
V
Table 5. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1) Forward transconductance VDS = 15v, ID = 2.6 A
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f = 1 MHz,
VGS = 0
Coss eq. Equivalent output
(2) capacitance
VDS =0V, VDS = 0V to 640V
5
1138
122
25
50
S
pF
pF
pF
pF
td(on)
tr
tr(off)
tr
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 400 V, ID = 2.6 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 16)
20 ns
12 ns
45 ns
20 ns
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 640 V, ID = 5.2 A,
VGS = 10 V
(see Figure 17)
40 56 nC
7 nC
21 nC
tr(Voff)
tr
tc
Off-voltage rise time
Fall time
Cross-over time
VDD = 640 V, ID = 5.2 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 16)
12 ns
10 ns
20 ns
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS.
5/18
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7NK80Z arduino
STP7NK80Z - STP7NK80ZFP - STB7NK80Z - STB7NK80Z-1
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/18
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