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HC374 PDF даташит

Спецификация HC374 изготовлена ​​​​«RCL Semiconductors» и имеет функцию, называемую «Tri-State Octal D-Type Flip-Flops».

Детали детали

Номер произв HC374
Описание Tri-State Octal D-Type Flip-Flops
Производители RCL Semiconductors
логотип RCL Semiconductors логотип 

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HC374 Даташит, Описание, Даташиты
Preliminary Specification
RCL Semiconductors Ltd.
Tri–State Octal D-Type Flip-Flops (Edge Triggered)
HC374
GENERAL DESCRIPTION
HC374 is fabricated in the high-speed silicon
gate CMOS technology. It has the high noise
immunity and low power consumption of standard
CMOS integrated circuits. It also offers speeds
comparable to low power Schottky devices
(LS-TTL).
These 8-bit flip-flops with 3-state outputs are
specifically designed for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bi-directional bus drivers, and
working registers.
HC374 has octal positive edge triggered
D-type flip-flops. On the positive transition of
the clock (CK) input, data at the inputs D,
meeting the setup and hold time requirement,
are transferred to the Q outputs.
FEATURES
• Wide operating supply voltage range: 2-6V
• Output Drive at VDD = 5V : ±6mA
• Typical propagation delay: 14ns
• Low input current: < 1µA
• Low quiescent supply current: 80µA maximum
• Octal D-type flip-flops in a single package
• Full Parallel access for Loading
An output-enable input (OE) places the
eight outputs in either a normal logic state (H
or L logic levels) or the high-impedance state.
In the high-impedance state, the outputs
neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive
bus lines without interface or pull-up
components.
OE does not affect the internal operation
of the flip-flops. Old data can be retained or
new data can be entered while the outputs
are in the high-impedance state.
OE should be tied to VDD through a pull-up
resistor to ensure the high-impedance state during
power up or power down,; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
LOGIC DIAGRAM
D1
3
D1
D2
4
D2
D3
7
D3
D4
8
D4
D5
13
D5
D6
14
D6
D7
17
D7
D8
18
D8
CK 11
C1 C2 C3 C4 C5 C6 C7 C8
1
OE
2
56
9
12 15
16 19
Q1
Q2 Q3
Q4
Q5 Q6
Q7 Q8
3 Dai Fu Street, Tai Po Industrial Estate, Tai Po, N.T. , Hong Kong.
Tel : (852)-26659229 Fax : (852)-26652201
1
070209
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HC374 Даташит, Описание, Даташиты
RCL Semiconductors Ltd.
FUNCTIONAL DESCRIPTION
Truth Table
Inputs
OE CK
L
L
L H or L
HX
D
H
L
X
X
H = High Level (steady state). L= Low Level (steady state)
X = Irrelevant (any input, including transitions)
= Transition from low to high level.
Z = high impedance state
Q0= The level of the output before steady state input conditions were established
HC374
Outputs
Q
H
L
Q0
Z
ABSOLUTE MAXIMUM RATINGS
Parameter
DC supply voltage (VDD)
DC input or output Voltage (VIN, VOUT)
DC Current Drain per pin, any output (Iout)
DC Current Drain per pin, VDD or GND (Icc)
Storage Temperature( TSTG)
Value
- 0.5 ~ + 7.0
-0.5 to VDD +0.5
±35
±70
-65 ~ +150
Unit
V
V
mA
mA
oC
Note: 1. Absolute maximum ratings are those values beyond which the safety of the device cannot be
guaranteed.
RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply Voltage (VDD)
VIH High-level Input Voltage
VIL Low-level Input Voltage
VI Input Voltage
VO Output Voltage
Operating Temperature (TA)
Input Rise/Fall Times
(tr, tf)
VDD=2.0V
VDD=4.5V
VDD=6.0V
VDD=2.0V
VDD=4.5V
VDD=6.0V
74HC374
54HC374
VDD=2.0V
VDD=4.5V
VDD=6.0V
Min.
2.0
1.5
3.15
4.2
0
0
-40
-55
Normal
5.0
Max.
6.0
0.5
1.35
1.8
VDD
VDD
+85
+125
1000
500
400
Unit
V
V
V
V
V
oC
oC
ns
Note: 2. All unused inputs of the device must be held at VDD or GND to ensure proper device operation.
RCL reserves the right to make changes to this specification at any time without notice
2
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HC374 Даташит, Описание, Даташиты
RCL Semiconductors Ltd.
DC ELECTRICAL CHARACTERISTICS
(unless otherwise specified)
HC374
Parameter
VOH
VOL
II
IOZ
Icc
Ci
Test Conditions
VI=VIH or VIL
IOH= -20µA
IOH= -6mA
IOH= -7.8mA
VI=VIH or VIL
VI=VDD or 0
VO =VDD or 0
VI=VDD or 0
IOL = 20µA
IOL = 6mA
IOL = 7.8mA
IO =0
VDD
TA =25 oC
54HC374 74HC374
Min. Typ. Max. Min. Max. Min. Max. Unit
2.0V 1.9 1.998 1.9 1.9
4.5V 4.4 4.499 4.4 4.4
6.0V 5.9 5.999 5.9 5.9
V
4.5V 3.98 4.3
3.7 3.84
6.0V 5.48 5.8
5.2 5.34
2.0V
0.002 0.1
0.1
0.1
4.5V
0.001 0.1
0.1
0.1
6.0V
0.001 0.1
0.1
0.1 V
4.5V
0.17 0.26
0.4
0.33
6.0V
0.15 0.26
0.4
0.33
6.0V
±0.1 ±100
±1000
±1000 nA
6.0V
±0.01 ±0.5
±10
±5 µA
6.0V
8 160 80 µA
2~6V
3 10
10
10 pF
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING TEMPERATURE RANGE
(unless otherwise noted)
Parameter
TA =25 oC
VDD Min. Max.
54HC374
74HC374
Min. Max. Min. Max.
Unit
2.0V
6
4
5
fclock
Clock frequency
4.5V
30
20
24 MHz
6.0V
35
24
28
2.0V 80
120 100
tw
Pulse duration, CK high or low
4.5V 16
24
20
ns
6.0V 14 20 17
2.0V 100 150 125
tsu Setup time, data before CK 4.5V 20 30 25 ns
6.0V 17 25 21
2.0V 10 13 12
th
Hold time, data after CK
4.5V 5
5
5
ns
6.0V 5 5 5
RCL reserves the right to make changes to this specification at any time without notice
3
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