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PDF 74HC374 Data sheet ( Hoja de datos )
| Número de pieza | 74HC374 | |
| Descripción | Octal 3-State Non-Inverting D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74HC374 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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74HC374
Octal 3−State Non−Inverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The 74HC374 is identical in pinout to the LS374. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374 is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
device is similar in function to the HC534A which has inverting
outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
• This is a Pb−Free Device
http://onsemi.com
MARKING
DIAGRAM
20
1
20
TSSOP−20
DT SUFFIX
CASE 948E
1
HC
374
ALYW G
G
HC374 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 0
1
Publication Order Number:
74HC374/D
http://www.Datasheet4U.com
1 page  
74HC374
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC – 55 to
(V)
25_C
v 85_C v 125_C Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
2.0 6 5 4 MHz
3.0 15
10
8
4.5 30 24 20
6.0 35 28 24
tPLH Maximum Propagation Delay, Input Clock to Q
tPHL (Figures 1 and 5)
2.0 125 155 190 ns
3.0 80
110 130
4.5 25 31 38
6.0 21 26 32
tPLZ Maximum Propagation Delay, Output Enable to Q
tPHZ
(Figures 3 and 6)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30 38 45
6.0 26 33 38
tPLZ Maximum Propagation Delay, Output Enable to Q
tPHZ
(Figures 3 and 6)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30 38 45
6.0 26 33 38
tTLH Maximum Output Transition Time, Any Output
tTHL (Figures 1 and 5)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
Cin Maximum Input Capacitance
Cout Maximum Three−State Output Capacitance
(Output in High−Impedance State)
10 10 10 pF
15 15 15 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Enabled Output)*
34 pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74HC374.PDF ] | |
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