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74VHC1G50 PDF даташит

Спецификация 74VHC1G50 изготовлена ​​​​«First Silicon» и имеет функцию, называемую «Noninverting Buffer / CMOS Logic Level Shifter».

Детали детали

Номер произв 74VHC1G50
Описание Noninverting Buffer / CMOS Logic Level Shifter
Производители First Silicon
логотип First Silicon логотип 

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74VHC1G50 Даташит, Описание, Даташиты
SEMICONDUCTOR
TECHNICAL D ATA
FC74VHC1G50
Noninverting Buffer / CMOS Logic Level Shifter
FC74VHC1G50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The FC74VHC1G50 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage.
This allows the 74VHC1G50 to be used to interface 5 V circuits to 3 V circuits.
High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V
Low Power Dissipation: I CC = 2 uA (Max) at TA = 25°C
TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V
CMOS–Compatible Outputs: V OH > 0.8 V CC ;
V OL < 0.1 V CC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 104; Equivalent Gates = 26
5
4
1
2
3
SC–70/SC–88A/SOT–353
DF SUFFIX
MARKING DIAGRAMS
VLd
Pin 1
d = Date Code
PIN ASSIGNMENT
1 NC
2 IN A
3 GND
4 OUT Y
5 V CC
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
201.09. 23
Revision No : 0
FUNCTION TABLE
Inputs
A
L
H
Output
Y
L
H
1/4
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74VHC1G50 Даташит, Описание, Даташиты
FC74VHC1G50
MAXIMUM RATINGS
Symbol
V CC
V IN
V OUT
I IK
I OK
I OUT
I CC
PD
θ JA
TL
TJ
T stg
V ESD
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V CC=0
High or Low State
Input Diode Current
Output Diode Current
DC Output Current, per Pin
V OUT < GND; V >OUT V CC
DC Supply Current, V CC and GND
Power dissipation in still air
Thermal resistance
Lead Temperature, 1 mm from Case for 10 s
Junction Temperature Under Bias
Storage temperature
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Value
– 0.5 to + 7.0
– 0.5 to +7.0
– 0.5 to +7.0
–0.5 to V cc + 0.5
–20
+20
+ 25
+50
200
333
260
+ 150
–65 to +150
>2000
> 200
N/A
Unit
V
V
V
mA
mA
mA
mA
mW
°C/W
°C
°C
°C
V
I LATCH–UP
Latch–Up Performance Above V CC and Below GND at 125°C (Note 5)
± 500
mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied. Functional operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
V CC DC Supply Voltage
V IN DC Input Voltage
V OUT
DC Output Voltage
T A Operating Temperature Range
t r ,t f
Input Rise and Fall Time
V CC = 0
High Low State
V CC = 3.3 ± 0.3 V
V CC = 5.0 ± 0.5 V
Min Max Unit
3.0 5.5 V
0.0 5.5 V
0.0 5.5 V
0.0 V CC
– 55
+ 125
°C
0 100 ns/V
0 20
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
80
90
100
110
120
130
140
Time,
Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time,
Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
1
1 10 100 1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
2011. 09. 23
Revision No : 0
2/4
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74VHC1G50 Даташит, Описание, Даташиты
FC74VHC1G50
DC ELECTRICAL CHARACTERISTICS
Symbol
V IH
Parameter
Minimum High–Level
Input Voltage
Test Conditions
V L Maximum Low–Level
Input Voltage
V OH Minimum High–Level V N = V H or V L
Output Voltage
I OH = – 50 µA
V N = V IH or V L
V N = V H or V L
I OH = –4 mA
I OH = –8 mA
V OL Maximum Low–Level
V N = V H or V L
Output Voltage
I OL = 50 µA
V N = V IH or V L
V N = V H or V L
I OL = 4 mA
I OL = 8 mA
I IN Maximum Input
V IN = 5.5 V or GND
Leakage Current
I CC Maximum Quiescent
V IN = V CC or GND
Supply Current
I CCT Quiescent Supply
Input: V IN = 3.4 V
Current
I OPD Output Leakage
V OUT = 5.5 V
Current
V CC T A = 25°C T A < 85°C –55°C<TA<125°C
(V) Min Typ Max Min Max Min Max Unit
2.0 1.5
1.5 1.5
V
3.0 2.1
2.1 2.1
4.5 3.15
3.15
3.15
5.5 3.85
3.85
3.85
2.0 0.5 0.5 0.5 V
3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
5.5 1.65 1.65 1.65
V
3.0 2.9 3.0
2.9 2.9
4.5 4.4 4.5
4.4 4.4
3.0 2.58
4.5 3.94
2.48 2.34
3.80 3.66
3.0 0.0 0.1 0.1 0.1
4.5 0.0 0.1 0.1 0.1
V
3.0
4.5
0 to5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
0.52
0.52
±1.0
µA
5.5 2.0 20 40 µA
5.5 1.35 1.50 1.65 mA
0.0
0.5 5.0
10 µA
AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns
Symbol Parameter
Test Conditions
T A = 25°C
T A < 85°C –55°C<TA<125°C
Min Typ Max Min Max Min Max Unit
t PLH ,
t PHL
Maximum
Propagation Delay,
Input A to Y
V CC = 3.3± 0.3 V C L = 15 pF
C L = 50 pF
4.5 10.0
6.3 13.5
11.0 13.0 ns
15.0 17.5
C N Maximum Input
Capacitance
V CC = 5.0± 0.5 V C L = 15 pF
C L = 50 pF
3.5 6.7
4.3 7.7
5 10
7.5 8.5
8.5 9.5
10 10 pF
C PD Power Dissipation Capacitance (Note 6)
Typical @ 2C, V CC = 5.0 V
12
pF
6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without
.load. Average operating current can be obtained by the equation: I CC(OPR) = C PD V CC f in + I CC C PD is used to determine the no–
load dynamic power consumption; P D = C PD V CC 2 f in + I CC V CC .
2011. 09. 23
Revision No : 0
3/4
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Номер в каталогеОписаниеПроизводители
74VHC1G50Noninverting Buffer / CMOS Logic Level ShifterFirst Silicon
First Silicon

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