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PDF NB638 Data sheet ( Hoja de datos )
| Número de pieza | NB638 | |
| Descripción | High Efficiency Fast Transient 7A 28V Synchronous Step-down Converter | |
| Fabricantes | MPS | |
| Logotipo |  |
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Sy
The Future of Analog IC Technology
NB638
High Efficiency, Fast Transient, 7A, 28V
nchronous Step-down Converter
in a Tiny 3x4mm QFN Package
DESCRIPTION
The NB638 is a fully integrated, high frequency
synchronous rectified step-down switch mode
converter. It offers a very compact solution to
achieve 7A continuous output cur rent over a
wide input supply range with excelle nt load an d
line regulation. The N B638 operates at high
efficiency over a wide ou tput current load range.
Constant-On-Time (COT) co
ntrol mod e
provides fast transient response and eases loop
stabilization.
Full protection features include SCP, OCP, OVP,
UVP and thermal shutdown.
The NB63 8 req uires a mi nimum number of
readily available sta ndard ext ernal components
and is ava ilable in a spa ce-saving QFN2 0
(3x4mm) package.
FEATURES
• Wide 4.5V to 28V Operating Input Range
• 7A Output Current
• Internal 30mΩ High-Side, 12mΩ Low-Side
Power MOSFETs
• Proprietary Switching Loss Reduction
Technique
• 1% Reference Voltage
• Programmable Soft Start Time
• Soft Shutdown
• 200kHz to 1MHz Switching Frequency
• SCP, OCP, OVP, UVP Protection and
Thermal Shutdown
• Output Adjustable from 0.8V to 13V
• Available in a QFN20 (3x4mm) Package
APPLICATIONS
• Notebook Systems and I/O Power
• Networking Systems
• Optical Communication Systems
• Distributed Power and POL Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
R7
8,19 IN
CIN
BST 7
C3
NB638 SW
2 FREQ
9,10,17,18
20 VCC
R4 C4
6 PGOOD
EN
5 EN
FB 3
SS AGND PGND
41
CSS
33nF
11-16
VOUT 1.05V
R1
C2
R2
NB638 Rev.1.16
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
http://www.Datasheet4U.com
1 page  
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB638 Rev.1.16
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
5
5 Page 
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
RESR
≥
TSTW
0.7 ×π
+
COUT
ON
2
(4)
Tsw is the switching period.
Ramp with small ESR Cap
When the output capa citors are ceramic ones,
the ESR ripple is not high enough t o stabilize the
system, an d external ramp co mpensation is
needed. Skip to application information sectio n
for design steps with small ESR caps.
SW L
Vo
R4 C4
IR4
R9
IC4
IFB
FB
R1
R2
Ceramic
limitation fr om equation 5, then we can only
reduce R4. For a stable PWM o peration, th e
Vslope1 should be design follow equation 9.
-Vslope1
≥
TSTW
0.7 ×
π
+
2L×
ON
2
-RESRCOUT
× COUT
VOUT
+
Io ×10−3
TSW -Ton
(9)
Io is the load current.
In skip mode, the downward slope of the V FB
ripple is almost the same wheth er the external
ramp is use d or not. Fig.9 shows t he simplifie d
circuit of th e skip mod e when both the HS-FET
and LS-FET are off.
Vo
FB R1
Cout Ro
R2
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
In PWM mode, an equivalent circu it with HS-FET
off and the use of an external ramp
compensation circuit ( R4, C4) is simplified in
Figure 7. The external ramp is derived from th e
inductor rip ple current. If one chooses C4, R9,
R1 and R2 to meet the following condition:
2Fπ×
11
SW × C4 <×5
⎛⎜⎝⎞⎟⎠RR11
×
+
R2
R2
+ R9
Where:
(5)
IRI 4 =+C≈4 IFIB C4
(6)
And the ra mp on the VFB can the n be est imated
as:
VRTAMP
=×VRIN4
− VO
×+C4
ON
×
R1/ / R2
R1 // R2 R9
(7)
The downward slope of the V FB ri pple t hen
follows
VSLOPE1
=
−VRAMP
ToRff
=
−VOUT
4 × C4
(8)
As can be seen from equation 8, if there is
instability in PWM mod e, we can r educe eith er
R4 or C4. If C4 can not be reduced further due to
Figure 8—Simplified Circuit in skip Mode
The downward slope o f the V FB ripple in skip
mode can be determined as follow:
( )VSLOPE2
=
(
R1
−VREF
+×R2 // Ro)
COUT
(10)
Where Ro is the equivalent load resistor.
As described in Fig.5, V SLOPE2 in the skip mode is
lower than that is in t he PWM mode, so it is
reasonable that the jitt er in the skip mode is
larger. If o ne wants a system wi th less jitter
during ultra light load co ndition, the values of the
VFB resistors should not be too big, however, that
will decrease the light load efficiency.
Soft Start/Stop
The NB63 8 employs soft start/stop (SS)
mechanism to ensure smooth o utput during
power-up and power shutdown. When the EN pin
becomes high, an internal current source (8.5 μA)
charges up the SS CAP. The SS CAP voltag e
takes over the REF voltage t
o the PWM
comparator. The output voltage smoothly ramp s
NB638 Rev.1.16
4/18/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet NB638.PDF ] | |
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