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PDF NB650 Data sheet ( Hoja de datos )
| Número de pieza | NB650 | |
| Descripción | High Efficiency Fast-Transient 6A 28V Synchronous Step-down Converters | |
| Fabricantes | MPS | |
| Logotipo |  |
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NB650/NB650H
High-Effeciency, Fast-Transient, 6A, 28V
Synchronous Step-Down Converters with 2-Bit VID
The Future of Analog IC Technology
DESCRIPTION
The NB650/NB650H is fully-integr ated, high-
frequency, synchronous, rectified, step-down,
switch-mode converters with dyn amic-output–
voltage control. It offers a very compact solution
to achieve 6A of continuous output current over
a wide inpu t supply ra nge, and h as excellent
load and line regulatio n. The NB6 50/NB650H
operates at high efficien cy over a wide output-
current–load range.
Constant-On-Time control mode provides fast
transient response and eases loop stabilization.
2-bit VID in puts suppor t changing the output
voltage on-the-fly.
Full protect ion features include short-circuit
protection, over-current protection, o ver-voltage
protection, under-voltage prot ection, an d
thermal shut down.
The NB650/NB650H requires a minimal number
of readily-available standard extern
al
components, and is available in a space-saving
3mm×4mm QFN17 package.
FEATURES
• Wide 4.5V-to-28V Operating Input Range
• 6A Output Current
• Internal 50mΩ High-Side, 18mΩ Low-Side
Power MOSFETs
• Proprietary Switching Loss Reduction
Technique
• 1% Reference Voltage
• Programmable Soft-Start Time
• 2-bit VID Input
• Soft Shutdown
• Frequency Programmable from 150kHz to
1MHz
• SCP, OCP, OVP, UVP, and Thermal
Shutdown
• Optional OCP Protection: Latch-Off Mode
(NB650) and Hiccup Mode (NB650H)
• Output Adjustable from 0.6V to 13V
• Available in QFN17 (3mm×4mm) Package
APPLICATIONS
• Notebook Systems and I/O Power
• Networking Systems
• Digital Set Top Boxes
• Flat-Panel Televisions and Monitors
• Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit M PS website u nder Q uality Assurance. “MPS” and “ The
Future of An alog IC Technology” a re Re gistered T rademarks of Mo nolithic
Power Systems, Inc.
TYPICAL APPLICATION （FOR NOTEBOOK）
VIN
C1
ON/OFF
R6
C5
ON/OFF
11
IN
R7
17 FREQ
5 EN
8 VCC
R5
4 PG
6
VID1
3
BST
1,2
SW
NB650
NB650H
FB 13
RFB2 14
RFB1 15
C3 L1
R4 C4
R2C R2B
ON/OFF
7
VID2
SS 16
PGND
9,10
GND
12
C6
R1
R2A
VOUT
C2
NB650/NB650H Rev. 1.12
www.MonolithicPower.com
10/11/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
http://www.Datasheet4U.com
1 page  
NB650/NB650H – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB650/NB650H Rev. 1.12
www.MonolithicPower.com
10/11/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
5
5 Page 
NB650/NB650H – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
Figure 7: Simplified Circuit in PWM Mode without
External Ramp Compensation
To realize the stability without the use of an
external ramp, select an ESR value as follows:
RESR
≥
tSW
0.7 ×π
+
COUT
tON
2
(4)
Where tSW is the switching period.
Ramp with Small ESR Capacitor
The ESR ripple when using ce ramic output
capacitors is not high enough to stabilize the
system and requires an external compensation
ramp. The applicatio n section includes a
description of de signing with small E SR
capacitors.
Figure 8: Simplified Circuit in PWM Mode with
External Ramp Compensation
Figure 7 sh ows a simplified equivalent circu it in
PWM mode with the HS-FET OFF and an
external ramp compensation circuit (R4, C4). The
external ramp is derived from the inductor rip ple
current. If one chooses C4, R9, R1 and R2 t o
meet the following condition:
11
2fπ× SW × C4 <×5
⎛⎜⎝⎞⎟⎠RR11
×
+
R2
R2
+ R9
(5)
Where:
IRI 4 =+C≈4 IFIB C4
(6)
And R2 is the equivalent resistor from FB to GND
that varies with VID input, the ra mp on the V FB
can then be estimated as:
VRtAMP
=×VRIN4
− VO
×+C4
ON
×
R1/ / R2
R1 // R2 R9
(7)
Usually R9 is set to 0 Ω, then equat ion 7 can be
simplified as:
VRAMP
=
(VIN − VO ) × τON
R4 × C4
(8)
The downward slope of the V FB ri pple t hen
follows
VSLOPE1
==−
VRAMP
tRoff
−VOUT
4 × C4
(9)
As shown in equation 8, if there is instability in
PWM mode, we can re duce either R4 or C4. I f
C4 can not be reduced further due to limitation s
from equation 5, then we can only reduce R4.
For a stable PWM operation, the Vslope1 should be
designed as follows.
-Vslope1
≥
ttSW
0.7 ×
π
+
2L×
ON
2
-RESRCOUT
× COUT
VOUT
+
Io ×10−3
tSW -ton
(10)
Where IO is the load current.
In skip mode, the downward slope of the V FB
ripple is almost the same with o r without the
external ramp. Figure 9 shows the simplified
circuit of th e skip mode when bot h HS-FET and
LS-FET are off.
Figure 9: Simplified Circuit in Skip Mode
The downward slope o f the V FB ripple in skip
mode can be determined as:
( )VSLOPE2
=
(R
1
−VREF
+×R2 // Ro)
COUT
(11)
NB650/NB650H Rev. 1.12
www.MonolithicPower.com
10/11/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet NB650.PDF ] | |
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