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NB3U23C PDF даташит

Спецификация NB3U23C изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «1.2V Dual Channel CMOS Buffer - Translator».

Детали детали

Номер произв NB3U23C
Описание 1.2V Dual Channel CMOS Buffer - Translator
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NB3U23C Даташит, Описание, Даташиты
NB3U23C
1.2 V Dual Channel CMOS
Buffer / Translator
Description
The NB3U23C is a 2−input, 2−output buffer/voltage translator for
UFS (Universal Flash Storage) in portable consumer applications such
as mobile phones, tablets, cameras, etc. This dual channel CMOS
buffer accepts 1.8 V CMOS input and translates it to 1.2 V CMOS
output. The device is powered using single supply of 1.2 V ±5%.
The NB3U23C is packaged in 2 ultra−small 6−pin packages: the 6
pin SC70 and a 6 pin thin UDFN package.
Features
Operating Frequency: 52 MHz (Max)
Propagation Delay: 5 ns (Max)
Low Standby Current: < 10 mA at 1.2 V VDD
Low Phase Noise Floor: −150 dBc/Hz (Typ)
Rise/Fall Times (tr/tf): 2 ns (Max)
ESD Protection Exceeds JEDEC Standards
2000 V Human−Body Model (JS−001−2012)
200 V Machine Model (JESD22−A115C)
1000 V Charged−Device Model (JESDC101E)
Operating Supply Voltage Range (VDD): 1.2 V ±5%
Operating Temperature Range (Industrial): −40°C to 85°C
These are Pb−Free Devices
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MARKING
DIAGRAMS
6
SC−70
SQ SUFFIX
1 CASE 419B
23CMG
G
1
23C = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
UDFN6
MN SUFFIX
CASE 517CW
C = Device Code
M = Date Code
CM
VDD
IN1 1
5
1
6 OUT1
IN2 3 2
2
4 OUT2
GND
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 6
1
Publication Order Number:
NB3U23C/D









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NB3U23C Даташит, Описание, Даташиты
NB3U23C
IN1 1
GND 2
IN2 3
SC70−6
Package
6 OUT1
5 VDD
4 OUT2
IN1 1
GND 2
IN2 3
UDFN6
Package
Figure 2. Pinout Diagram (Top Views)
6 OUT1
5 VDD
4 OUT2
Table 1. PIN DESCRIPTION
Number
Name
1 IN1
2 GND
3 IN2
4 OUT2
5 VDD
6 OUT1
Input Clock Signal − Channel 1
Power Supply Ground (0 V)
Input Clock Signal − Channel 2
Output − Channel 2
Power Supply Voltage
Output − Channel 1
Description
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Charge Device Model
Moisture Sensitivity (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test II
1. For additional information, see Application Note AND8003/D.
Value
2 kV min
200 V min
1 kV min
Level 1
UL 94 V−0 @ 0.125 in
120
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NB3U23C Даташит, Описание, Даташиты
NB3U23C
Table 3. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VDD Supply Voltage
Vin Input Voltage
ID Output Current
TA Operating Temperature Range, Industrial
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm (Note 3)
0 lfpm
500 lfpm (Note 3)
SC70−6
UDFN−6
3.6
–0.5 VI 2.5
25
−40 to +85
−65 to +150
210
126
245
172
V
V
mA
°C
°C
°C/W
qJC Thermal Resistance (Junction−to−Case)
(Note 3)
SC70−6
UDFN−6
100 °C/W
150
Tsol Wave Solder
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 4. ELECTRICAL CHARACTERISTICS (VDD = 1.2 ±5% V, GND = 0 V, TA = −40°C to +85°C)
Symbol
Characteristic
Conditions
Min Typ Max Unit
DIDD
Ioff
VIH
VIL
VOH
VOL
Cin
Fclk
tPD
Power Supply Current
(Single Channel Switching @ 52 MHz)
Power Supply Current
(Both Channels Switching @ 52 MHz)
Standby Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Operating Frequency Range
Propagation Delay
Phase Noise Floor Density
(Notes 4 and 5)
Additive RMS Phase Jitter
(Notes 5 and 6)
CL = 20 pF
CL = 5 pF
CL = 1 pF
CL = 20 pF
CL = 5 pF
CL = 1 pF
Vi = VIH Max or GND;
VDD = 1.2 V, No Output Load
CL = 20 pF
RL = 100 kW
CL = 20 pF
RL = 100 kW
INx to OUTx
CL = 20 pF, RL = 100 kW
CL = 20 pF
RL = 100 kW
CL = 20 pF
RL = 100 kW
Offset Frequency Range:
50 kHz to 10 MHz
0.65 * VDD
0
0.75 * VDD
0
0
2.5
1.5
1
5
3
2
−150
0.15
mA
mA
10 mA
1.98
0.35 * VDD
VDD
V
V
V
0.25 * VDD
V
5 pF
52 MHz
5 ns
dBc/Hz
0.25 ps
DC Output Duty Cycle (Note 7)
Input Duty Cycle = 50%,
Min Input Slew Rate = 1 V/ns
45
55 %
tr/tf Output Rise/Fall Times
0.2 * VDD to 0.8 * VDD
CL = 20 pF
RL = 100 kW
2 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. White noise floor.
5. This parameter refers to the random jitter only.
6. The output RMS phase jitter can be calculated using the following equation:
(Output RMS Phase Jitter)2 = (Input RMS Phase Jitter)2 + (Additive RMS Phase Jitter)2
7. Measured with input voltage swing from 0 V to 1.8 V.
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Номер в каталогеОписаниеПроизводители
NB3U23C1.2V Dual Channel CMOS Buffer - TranslatorON Semiconductor
ON Semiconductor

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