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ATSAM4L2 Datasheet Download - Atmel

Номер произв ATSAM4L2
Описание Flash MCU
Производители Atmel
логотип Atmel логотип 

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ATSAM4L2 Даташит, Описание, Даташиты
Summary
Atmel's SAM4L series is a member o f a family of Flash microcontrollers based
on the high performance 32-bit ARM Cortex-M4 RISC processor running at fre-
quencies up to 48MHz.
The SAM4L series embeds state-of-the-art picoPower technology for ultra-low
power consumption. Combined power control techniques are used to bring
active current consumption down to 90µA/MHz. The device allows a wide range
of options be tween functionalit y and po wer consumpt ion, giving the u ser th e
ability to rea ch the l owest poss ible power consumpt ion wi th t he feature set
required for the application. The WAIT and RETENTION modes provide full logic
and RAM retention, associated with fast wake-up capability (<1.5µs) and a very
low consumption of, respectively, 3 µA and 1.5 µA. In addition, WAIT mode sup-
ports SleepWalking features. In BACKUP mode, CPU, peripherals and RAM are
powered off and, while consuming less than 0.9µA with external interrupt wake-
up supported.
The SAM4L series offers a wide range of peripherals such as segment LCD con-
troller, embedded hardware capacitive touch (QTouch), USB device & embedded
host, 128-bit AES and audio interfaces in addition to high speed serial peripher-
als such as USART, SPI and I 2C. Additionally the Peripheral Event System and
SleepWalking allo ws the peripherals to comm unicate direc tly with each other
and make intelligent decisions and decide to wake-up the system on a qualified
events on a peripheral level; such as I2C address match or and ADC threshold.
ATSAM---e
ARM-based
Flash MCU
SAM4L Series
Features
Core
– ARM® CortexTM-M4 running at up to 48MHz
– Memory Protection Unit (MPU)
–T humb®-2 instruction set
picoPower® Technology for Ultra-low Power Consumption
– Active mode downto 90µA/MHz with configurable voltage scaling
– High performance and efficiency: 28 coremark/mA
– Wait mode downto 3µA with fast wake-up time (<1.5µs) supporting SleepWalking
– Full RAM and Logic Retention mode downto 1.5µA with fast wake-up time (<1.5µs)
– Ultra low power Backup mode with/without RTC downto 1,5/0.9µA
Memories
– From 128 to 512Kbytes embedded Flash, 64-bit wide access,
• 0 wait-state capability up to 24MHz
– up to 64Kbytes embedded SRAM
System Functions
– Embedded voltage linear and switching regulator for single supply operation
– Two Power-on-Reset and Two Brown-out Detectors (BOD)
– Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure
Detection and low power 32.768 kHz for RTC or device clock
– High precision 4/8/12MHz factory trimmed internal RC oscillator
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– High speed 80MHz internal RC oscillator
– Low power 32kHz internal RC oscillator
– PLL up to 240MHz for device clock and for USB
Summary
42023GS–03/2014
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ATSAM4L2 Даташит, Описание, Даташиты
ATSAM4L8/L4/L2
– Digital Frequency Locked Loop (DFLL) with wide input range
– Up to 16 peripheral DMA (PDCA) channels
Peripherals
– USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode. On-
Chip Transceiver
– Liquid Crystal Display (LCD) Module with Capacity up to 40 Segments and up to 4 Common Terminals
– One USART with ISO7816, IrDA®, RS-485, SPI, Manchester and LIN Mode
– Three USART with SPI Mode
– One PicoUART for extended UART wake-up capabilities in all sleep modes
– Windowed Watchdog Timer (WDT)
– Asynchronous Timer (AST) with Real-time Clock Capability, Counter or Calendar Mode Supported
– Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
– Six 16-bit Timer/Counter (TC) Channels with capture, waveform, compare and PWM mode
– One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
– Four Master and Two Slave Two-wire Interfaces (TWI), up to 3.4Mbit/s I2C-compatible
– One Advanced Encryption System (AES) with 128-bit key length
– One 16-channel ADC 300Ksps (ADC) with up to 12 Bits Resolution
– One DAC 500Ksps (DACC) with up to 10 Bits Resolution
– Four Analog Comparators (ACIFC) with Optional Window Detection
– Capacitive Touch Module (CATB) supporting up to 32 buttons
– Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio
– Inter-IC Sound (IISC) Controller, Compliant with Inter-IC Sound (I2S) Specification
– Peripheral Event System for Direct Peripheral to Peripheral Communication
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Random generator (TRNG)
– Parallel Capture Module (PARC)
– Glue Logic Controller (GLOC)
I/O
– Up to 75 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and slew-rate
control
– Up to Six High-drive I/O Pins
Single 1.68-3.6V Power Supply
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball VFBGA, 7x7 mm, pitch 0.65 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 64-ball WLCSP, 4,314x4,434 mm, pitch 0.5 mm for SAM4LC4/2 and SAM4LS4/2 series
– 64-ball WLCSP, 5,270x5,194 mm, pitch 0.5 mm for SAM4LC8 and SAM4LS8 series
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
42023GS–SAM–03/2014
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ATSAM4L2 Даташит, Описание, Даташиты
ATSAM4L8/L4/L2
1. Description
Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high per-
formance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern and real-time operating systems.
The ATSAM4L8/L4/L2 embeds state-of-the-art picoPower technology for ultra-low power con-
sumption. Com bined powe r con trol tech niques are used to bring active curr ent consumption
down to 90µA/MHz. The device allows a wide range of options between functionality and power
consumption, giving the user the ability to reach the lowest possible power consumption with the
feature set required for the application. On-chip regulator improves power efficiency when used
in swichting mode with an external inductor or can be used in linear mode if application is noise
sensitive.
The ATSAM 4L8/L4/L2 supports 4 p ower saving strategies. The SLEEP mode put the CPU in
idle mode and offers different sub-modes which automatically switch off/on bus clocks, PLL,
oscillators. The WAIT and RETENTION modes provide full logic and RAM retention, associated
with fast wake-up capability (<1.5µs) and a very low c onsumption of, respectively, 3 µA and 1.5
µA. In addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, peripher-
als and RAM are powered off and, while consuming less than 0.5µA, the device is able to wake-
up from external interrupts.
The ATSAM4L8/L4/L2 incorporates on-chip Flash tig htly coupled to a low power cache
(LPCACHE) for active consumption optimization and SRAM memories for fast access.
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4
Common terminals and up to 40 Segments term inals. Ded icated Low Power Waveform, Con-
trast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink functionality are
supported to offload the CPU, reduce interrupts and reduce power con sumption. The controller
includes integrated LCD buffers and integrated power supply voltage.
The low-power and high performance capacitive touch module (CATB) is introduced to meet the
demand for a low power capacitive touch solution that could be used to handle but tons, sliders
and whe els. The CAT B provides excellent si gnal perf ormance, as well as autonomous touch
and proximity detection for up to 32 sensors. This solution includes an advanced sequencer in
addition to an hardware filtering unit.
The Adva nced Encryption Stan dard modu le (AESA) is compliant with the FIPS (Feder al Infor-
mation Processing St andard) Publicat ion 197, Advan ced Encr yption Stan dard (AES) , which
specifies a symmetric block ciphe r that is used to encr ypt and decrypt electronic data. Encryp-
tion is the transforma tion of a usable message , called t he plaintext , into an unr eadable f orm,
called the ciphertext. On the other hand, decryption is the transformation that recovers the plain-
text from the ciphertext. AESA supports 128 bits cryptographic key sizes.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories wit hout processor involveme nt. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The Peripheral Event System (PES) allows peripherals to receive, react to, and send peripheral
events without CPU intervention. Asynchronous interrupts allow advanced peripheral operat ion
in low power modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
42023GS–SAM–03/2014
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