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Номер произв ADF4155
Описание Integer-N/Fractional-N PLL Synthesizer
Производители Analog Devices
логотип Analog Devices логотип 

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ADF4155 Даташит, Описание, Даташиты
Data Sheet
Integer-N/Fractional-N PLL Synthesizer
ADF4155
FEATURES
GENERAL DESCRIPTION
Input frequency range: 500 MHz to 8000 MHz
The ADF4155 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer
integer-N phase-locked loop (PLL) frequency synthesizers
Phase frequency detector (PFD) up to 125 MHz
when used with an external loop filter, external voltage
High resolution 38-bit modulus
controlled oscillator (VCO), and external reference frequency.
Separate charge pump supply (VP) allows extended tuning
voltage in 5 V systems
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Differential and single-ended reference inputs
Power supply: 3.3 V ± 5%
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler (P) of 4/5 or 8/9
The ADF4155 is for use with external VCO parts up to an
8 GHz operating frequency. The high resolution programmable
modulus allows synthesis of exact frequencies with 0 Hz error.
The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to
allow the user to generate RF output frequencies as low as
7.8125 MHz.
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Control of all on-chip registers is through a simple 3-wire
interface. The device operates with a nominal power supply of
3.3 V ± 5% and can be powered down when not in use.
APPLICATIONS
The ADF4155 is available in a 24-lead, 4 mm × 4 mm LFCSP
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
package.
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RFVDD
RSET
REFIN+
REFIN
CLK
DATA
LE
CE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
ADF4155
÷ 1/2/4/8/16/32/64
MUXOUT
CPOUT
CREG1
CREG2
OUTPUT
STAGE
RFOUT +
RFOUT
PDBRF
INPUT
STAGE
RFIN +
RFIN
AGND
DGND
CPGND
Figure 1.
RFGND
Rev. 0
Document Feedback
Information furnished by Analog D evices is believedto be accurate and reliable. However, n o
responsibilityis assumedby Analog Devicesfor itsuse, nor for any infringementsof patents or other
rightsofthirdparties thatmay resultfrom its use.Specificationssubject tochangewithout notice.No
license is grantedby implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks are ht e propertyof their respective owners.
One T echnology Wa y, P .O. Box 9 106, Norwood, M A 02 062-9106, U .S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
http://www.Datasheet4U.com







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ADF4155 Даташит, Описание, Даташиты
ADF4155
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Circuit Description......................................................................... 12
Reference Input Section............................................................. 12
RF N Counter.............................................................................. 12
Phase Frequency Detector and Charge Pump ........................... 13
MUXOUT and Lock Detect...................................................... 13
Input Shift Registers ................................................................... 13
Program Modes .......................................................................... 13
Output Stage................................................................................ 14
REVISION HISTORY
4/14—Revision 0: Initial Version
Data Sheet
Register Maps.................................................................................. 15
Register 0 ..................................................................................... 17
Register 1 ..................................................................................... 18
Register 2 ..................................................................................... 19
Register 3 ..................................................................................... 19
Register 4 ..................................................................................... 20
Register 5 ..................................................................................... 22
Register 6 ..................................................................................... 23
Register 7 ..................................................................................... 24
Register 8 ..................................................................................... 25
Register Initialization Sequence ............................................... 26
RF Synthesizer—A Worked Example ...................................... 26
Reference Doubler and Reference Divider ............................. 27
Cycle Slip Reduction for Faster Lock Times........................... 27
Spurious Optimization .............................................................. 27
Spur Mechanisms ....................................................................... 27
Applications Information .............................................................. 28
Local Oscillator with RF Buffer................................................ 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
Rev. 0 | Page 2 of 32







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ADF4155 Даташит, Описание, Даташиты
Data Sheet
ADF4155
SPECIFICATIONS
AVDD = DVDD = RFVDD = 3.3 V ± 5%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = RFGND = CPGND = 0 V, and TA = TMIN to TMAX, unless otherwise
noted. Operating temperature range is −40°C to +85°C.
Table 1.
Parameter
REFIN+\REFIN− CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
PHASE DETECTOR
Phase Detector Frequency
RFIN+\RFIN− CHARACTERISTICS
RF Input Frequency
Prescaler Output Frequency
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
RSET Range
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output High Current, IOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
DVDD
RFVDD
VP
IP
Output Dividers
Min Typ Max Unit
10 250 MHz
10 600 MHz
0.7
AVDD
V p-p
0.4 1.8 V p-p
6.9 pF
1.4 pF
±60 µA
125 MHz
100 MHz
125 MHz
75 MHz
0.5 6.0 GHz
8.0 GHz
1.5 GHz
5
0.31
2.7 4.7
3
3
1.5
1.5
3.0
DVDD − 0.4
3.135
AVDD
AVDD
AVDD
4.1
6 to 36
10
0.6
±1
500
0.4
3.465
5.5
mA
mA
%
%
%
V
V
µA
pF
V
µA
V
V
V
V
V
mA
mA
Rev. 0 | Page 3 of 32
Test Conditions/Comments
For f < 10 MHz, ensure slew rate > 21 V/µs
REFIN+ biased at AVDD/2; ac coupling ensures
AVDD/2 bias
LVDS and LVPECL compatible, REFIN+\REFIN
biased at 2.1 V; ac coupling ensures 2.1 V bias
Negative bleed on
Pulsed bleed on
Negative bleed off and pulsed bleed off
CSR enabled
For lower frequencies, ensure that the slew
rate > 400 V/µs
−10 dBm minimum/0 dBm maximum
−5 dBm minimum/0 dBm maximum
RSET = 4.7 kΩ
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = 2.5 V
Compatible with 1.8 V and 3 V logic
CMOS output selected
IOL = 500 µA
Voltage must equal AVDD
Voltage must equal AVDD
Each output divide by 2 consumes 6 mA; see
Table 6 for details on the current consumption
as a function of the output power and divider










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