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PDF S1D13505F00A Data sheet ( Hoja de datos )
| Número de pieza | S1D13505F00A | |
| Descripción | Embedded RAMDAC LCD/CRT Controller | |
| Fabricantes | Epson Electronics | |
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PF937-04
S1D13505F00A
Embedded RAMDAC LCD/CRT Controller
s DESCRIPTION
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and
display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the
embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of
differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelViewTM
feature. Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while
the Hardware Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance
benefits. These features, combined with the S1D13505's Operating System independence, make it an ideal
display solution for a wide variety of applications.
s FEATURES
x Memory Interface
• 16-bit DRAM interface:
- EDO-DRAM up to 40MHz data rate (80M bytes
per second).
- FPM-DRAM up to 25MHz data rate (50M bytes
per second).
• Memory size options:
- 512K bytes using one 256K x 16 device.
- 2M bytes using one 1M x 16 device.
• Performance Enhancement Register to tailor the
memory control output timing for the DRAM
device.
x CPU Interface
• Supports the following interfaces:
- 8/16-bit SH-4 bus interface.
- 8/16-bit SH-3 bus interface.
- 8/16-bit interface to 8/16/32-bit MC68000
microprocessors/microcontrollers.
- 8/16-bit interface to 8/16/32-bit MC68030
microprocessors/microcontrollers.
- Philips PR31500/PR31700 (MIPS).
- Toshiba TX3912 (MIPS).
- Philips PR31500/PR31700.
- 16-bit Power PC (MPC821) microprocessor.
- 16-bit Epson E0C33 microprocessor.
- PC Card (PCMCIA).
- StrongARM (PC Card).
- NEC VR41xx (MIPS).
- ISA bus.
• Supports the following interface with external
logic:
- GX486 microprocessor.
• One-stage write buffer for minimum wait-state
CPU writes.
• Registers are memory-mapped - the M/R# pin
selects between the display buffer and register
address space.
• The complete 2M byte display buffer address
space is addressable as a single linear address
space through the 21-bit address bus.
x Display Support
• 4/8-bit monochrome passive LCD interface.
• 4/8/16-bit color passive LCD interface.
• Single-panel, single-drive displays.
• Dual-panel, dual-drive displays.
• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/
D-TFD is supported up to 64K color depth (16-bit
data).
• Embedded RAMDAC (DAC)with direct analog
CRT drive.
• Simultaneous display of CRT and passive or TFT/
D-TFD panels.
x Display Modes
• 1/2/4/8/15/16 bit-per-pixel (bpp) support on LCD/
CRT.
• Up to 16 shades of gray using FRM on
monochrome passive LCD panels.
• Up to 4096 colors on passive LCD panels; three
256x4 Look-Up Tables (LUT) are used to map 1/
2/4/8 bpp modes into these colors, 15/16 bpp
modes are mapped directly using the 4 most
significant bits of the red, green and blue colors.
• Up to 64K colors on TFT/D-TFD LCD panels and
CRT; three 256x4 Look-Up Tables are used to
map 1/2/4/8 bpp modes into 4096 colors, 15/16
bpp modes are mapped directly.
1
1 page  
S1D13505F00A
Generic
BUS
A[27:21]
CSn#
A[20:0]
D[15:0]
WE0#
WE1#
RD#
WAIT#
BCLK
RESET#
Decoder
Power
Management
Oscillator
M/R#
CS#
AB[20:0]
DB[15:0]
WE0#
WE1#
RD#
RD/WR#
WAIT#
BUSCLK
RESET#
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
S1D13505F00A
FPFRAME
FPLINE
DRDY
LCDPWR
RED,GREEN,BLUE
HRTC
VRTC
IREF
UD[7:0]
LD[7:0]
FPSHIFT 4/8/16-bit
LCD
FPFRAME Display
FPLINE
MOD
CRT
Display
IREF
1Mx16
FPM/EDO-DRAM
Typical System Diagram (Generic Bus, 1Mx16 FPM/EDO-DRAM)
MIPS
BUS
A[25:21]
CSn#
A[20:0]
D[15:0]
MEMW#
SBHE#
MEMR#
RDY
BCLK
RESET
Power
Management
Oscillator
Decoder
M/R#
CS#
AB[20:0]
DB[15:0]
VDD
WE0#
WE1#
RD#
RD/WR#
WAIT#
BUSCLK
RESET#
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
S1D13505F00A
FPFRAME
FPLINE
DRDY
LCDPWR
RED,GREEN,BLUE
HRTC
VRTC
IREF
UD[7:0]
LD[7:0]
FPSHIFT 4/8/16-bit
LCD
FPFRAME Display
FPLINE
MOD
CRT
Display
IREF
1Mx16
FPM/EDO-DRAM
Typical System Diagram (NEC VR41xx (MIPS) Bus, 1Mx16 FPM/EDO-DRAM)
5
5 Page 
S1D13505F00A
x Pin Description
Key:
I
O
I/O
A
P
C
CD
CS
COx
TSx
TSxD
CNx
= Input
= Output
= Bi-Directional (Input/Output)
= Analog
= Power pin
= CMOS level input
= CMOS level input with pull down resistor (typical values of 100KΩ/180KΩ at 5V/3.3V
respectively)
= CMOS level Schmitt input
= CMOS output driver, x denotes driver type (see tables “Electrical Characteristics for VDD =
5.0V Typical,” “Electrical Characteristics for VDD = 3.3V Typical,” “Electrical Characteristics
for VDD = 3.0V Typical” for details)
= Tri-state CMOS output driver, x denotes driver type (see tables “Electrical Characteristics for
VDD = 5.0V Typical,” “Electrical Characteristics for VDD = 3.3V Typical,” “Electrical
Characteristics for VDD = 3.0V Typical” for details)
= Tri-state CMOS output driver with pull down resistor (typical values of 100KW/180KW at 5V/
3.3V respectively), x denotes driver type (see tables “Electrical Characteristics for VDD =
5.0V Typical,” “Electrical Characteristics for VDD = 3.3V Typical,” “Electrical Characteristics
for VDD = 3.0V Typical” for details)
= CMOS low-noise output driver, x denotes driver type (see tables “Electrical Characteristics
for VDD = 5.0V Typical,” “Electrical Characteristics for VDD = 3.3V Typical,” “Electrical
Characteristics for VDD = 3.0V Typical” for details)
11
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