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HD3-6402B-9 PDF даташит

Спецификация HD3-6402B-9 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Universal Asynchronous Receiver Transmitter (UART)».

Детали детали

Номер произв HD3-6402B-9
Описание CMOS Universal Asynchronous Receiver Transmitter (UART)
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HD3-6402B-9 Даташит, Описание, Даташиты
TM HD-6402
March 1997
CMOS Universal Asynchronous
Receiver Transmitter (UART)
Features
• 8.0MHz Operating Frequency (HD-6402B)
• 2.0MHz Operating Frequency (HD-6402R)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
Description
The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when transmit-
ting 5-bit code.
The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements, by compar-
ison, are reduced from 300mW to 10mW. Status logic
increases flexibility and simplifies the user interface.
Ordering Information
PACKAGE
Plastic DIP
CERDIP
SMD#
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
-55oC to +125oC
2MHz = 125K BAUD
HD3-6402R-9
HD1-6402R-9
5962-9052501MQA
8MHz = 500K BAUD
HD3-6402B-9
HD1-6402B-9
5962-9052502MQA
PKG. NO.
E40.6
F40.6
F40.6
Pinout
HD-6402 (PDIP, CERDIP)
TOP VIEW
VCC 1
NC 2
GND 3
RRD 4
RBR8 5
RBR7 6
RBR6 7
RBR5 8
RBR4 9
RBR3 10
RBR2 11
RBR1 12
PE 13
FE 14
OE 15
SFD 16
RRC 17
DRR 18
DR 19
RRI 20
40 TRC
39 EPE
38 CLS1
37 CLS2
36 SBS
35 PI
34 CRL
33 TBR8
32 TBR7
31 TBR6
30 TBR5
29 TBR4
28 TBR3
27 TBR2
26 TBR1
25 TRO
24 TRE
23 TBRL
22 TBRE
21 MR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
1
File Number 2956.1









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HD3-6402B-9 Даташит, Описание, Даташиты
Functional Diagram
(24) TRE
(22) TBRE
(23) TBRL
(40) TRC
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
(17) RRC
(18) DRR
(19) DR
TRANSMITTER
TIMING AND
CONTROL
RECEIVER
TIMING AND
CONTROL
(16) SFD
THESE OUTPUTS ARE
THREE-STATE
OE
(15)
HD-6402
(32) (30) (28) (26)
TBR8 (33) (31) (29) (27) TBR1
STOP
PARITY
LOGIC
TRANSMITTER BUFFER REGISTER
TRANSMITTER REGISTER
MULTIPLEXER
START
CONTROL
REGISTER
STOP
LOGIC
FE
(14)
MULTIPLEXER
PARITY
LOGIC
RECEIVER REGISTER
RECEIVER BUFFER REGISTER
START
LOGIC
3-STATE
BUFFERS
PE
(13)
RBR8
RBR1
(5) (6) (7) (8) (9) (10) (11) (12)
(25) TRO
(36) SBS
(16) SFD
(39) EPE
(35) PI
(20) RRI
(4) RRD
Control Definition
CLS 2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
CONTROL WORD
CLS 1
PI
EPE
000
000
001
001
0 1X
0 1X
100
100
101
101
1 1X
11x
000
000
001
001
0 1X
01x
100
100
101
101
1 1X
11x
SBS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
START BIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CHARACTER FORMAT
DATA BITS
PARITY BIT
5 ODD
5 ODD
5 EVEN
5 EVEN
5 NONE
5 NONE
6 ODD
6 ODD
6 EVEN
6 EVEN
6 NONE
6 NONE
7 ODD
7 ODD
7 EVEN
7 EVEN
7 NONE
7 NONE
8 ODD
8 ODD
8 EVEN
8 EVEN
8 NONE
8 NONE
STOP BITS
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2









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HD3-6402B-9 Даташит, Описание, Даташиты
HD-6402
Pin Description
PIN TYPE SYMBOL
DESCRIPTION
1 VCC Positive Voltage Supply
2 NC No Connection
3 GND Ground
4I
RRD
A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.
5O
RBR8
The contents of the RECEIVER BUFFER REGIS-
TER appear on these three-state outputs. Word for-
mats less than 8 characters are right justified to
RBR1.
6 O RBR7 See Pin 5-RBR8
7 O RBR6 See Pin 5-RBR8
8 O RBR5 See Pin 5-RBR8
9 O RBR4 See Pin 5-RBR8
10 O RBR3 See Pin 5-RBR8
11 O RBR2 See Pin 5-RBR8
12 O RBR1 See Pin 5-RBR8
13 O
PE A high level on PARITY ERROR indicates received
parity does not match parity programmed by control
bits. When parity is inhibited this output is low.
14 O
FE A high level on FRAMING ERROR indicates the
first stop bit was invalid.
15 O
OE A high level on OVERRUN ERROR indicates the
data received flag was not cleared before the last
character was transferred to the receiver buffer
register.
16 I
SFD
A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
17 I
RRC The Receiver register clock is 16X the receiver
data rate.
18 I
DRR A low level on DATA RECEIVED RESET clears
the data received output DR to a low level.
19 O
DR A high level on DATA RECEIVED indicates a
character has been received and transferred to
the receiver buffer register.
20 I
RRI Serial data on RECEIVER REGISTER INPUT is
clocked into the receiver register.
21 I
MR A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiv-
er buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
VIH and tMR. Wait 18 clock cycles after the falling
edge of MR before beginning operation.
22 O
TBRE
A high level on TRANSMITTER BUFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has transferred its data to the transmitter register
and is ready for new data.
23 I
TBRL
A low level on TRANSMITTER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
high transition on TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
transmitted end to end.
PIN TYPE SYMBOL
DESCRIPTION
24 O
TRE
A high level on TRANSMITTER REGISTER EMP-
TY indicates completed transmission of a charac-
ter including stop bits.
25 O
TRO Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
26 I
TRB1
Character data is loaded into the TRANSMITTER
BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro-
grammed word length.
27 I
TBR2 See Pin 26-TBR1.
28 I
TBR3 See Pin 26-TBR1.
29 I
TBR4 See Pin 26-TBR1.
30 I
TBR5 See Pin 26-TBR1.
31 I
TBR6 See Pin 26-TBR1.
32 I
TBR7 See Pin 26-TBR1.
33 I
TBR8 See Pin 26-TBR1.
34 I
CRL
A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
35 I
PI A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
36 I
SBS
A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
37 I
CLS2
These inputs program the CHARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)
38 I
CLS1 See Pin 37-CLS2.
39 I
EPE
When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A low
level selects odd parity.
40 I
TRC The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
A 0.1µF decoupling capacitor from the VCC pin to the GND is rec-
ommended.
3










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