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HD4-15530-8 PDF даташит

Спецификация HD4-15530-8 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Manchester Encoder-Decoder».

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Номер произв HD4-15530-8
Описание CMOS Manchester Encoder-Decoder
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HD4-15530-8 Даташит, Описание, Даташиты
HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
PDIP
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
1.25 MEGABIT/s PKG. NO.
HD1-15530-9
F24.6
HD1-15530-8
7802901JA
HD4-15530-9
J28.A
HD4-15530-8
78029013A
HD3-15530-9
E24.6
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for the
Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Pinouts
HD-15530 (CERDIP, PDIP)
TOP VIEW
VALID WORD 1
ENCODER
SHIFT CLK
2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC
10
DECODER RESET 11
GND 12
24 VCC
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15
BIPOLAR
ZERO OUT
14 ÷ 6 OUT
13 MASTER RESET
HD-15530 (CLCC)
TOP VIEW
4 3 2 1 28 27 26
DECODER
CLK
5
25
SEND
DATA
NC 6
24 NC
NC 7
23 NC
BIPOLAR
ZERO IN
8
22
SYNC
SELECT
BIPOLAR
ONE IN
9
21
ENCODER
ENABLE
UNIPOLAR
DATA IN
10
20
SERIAL
DATA IN
DECODER
SHIFT CLK
11
19
BIPOLAR
ONE OUT
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-142
File Number 2960.1









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HD4-15530-8 Даташит, Описание, Даташиты
HD-15530
Block Diagrams
ENCODER
12 GND
MASTER RESET
13
SEND CLK IN
22
14 ÷ 6 OUT
÷2
÷6
VCC 24
OUTPUT
INHIBIT
16
17 BIPOLAR
CHARACTER
ONE OUT
FORMER
BIPOLAR
15 ZERO OUT
ENCODER
CLK
23
BIT
COUNTER
18 19
2
21 SERIAL
20
SYNC
SEND DATA IN
SELECT
DATA
ENCODER
ENABLE
ENCODER
SHIFT CLK
DECODER
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
8
7
6
TRANSITION
FINDER
DECODER 5 SYNCHRONIZER
CLK
CHARACTER
IDENTIFIER
3 TAKE
DATA
10 COMMAND/
DATA SYNC
4 SERIAL
DATA OUT
BIT
RATE
CLK
PARITY 1 VALID
CHECK WORD
MASTER 13
RESET
DECODER 11
BIT
RESET
COUNTER
9 DECODER
SHIFT
CLK
Pin Description
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TYPE
NAME
O VALID WORD
O ENCODER SHIFT
CLOCK
O TAKE DATA
O SERIAL DATA OUT
I DECODER CLOCK
I BIPOLAR ZERO IN
I BIPOLAR ONE IN
I UNLPOLAR DATA IN
O DECODER SHIFT
CLOCK
O COMMAND SYNC
I DECODER RESET
I GROUND
I MASTER RESET
O ÷ 6 OUT
O BIPOLAR ZERO OUT
I OUTPUT INHIBIT
O BIPOLAR ONE OUT
SECTION
DESCRIPTION
Decoder Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
Encoder Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
Decoder Output is high during receipt of data after identification of a sync pulse and
two valid Manchester data bits.
Decoder Delivers received data in correct NRZ format.
Decoder
Input drives the transition finder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
Decoder A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
Decoder A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
Decoder With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
Decoder Output which delivers a frequency (DECODER CLOCK ÷ 12), synchro-
nized by the recovered serial data stream.
Decoder
Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
Decoder A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
Both Ground Supply pin.
Both
A high on this pin clears 2:1 counters in both Encoder and Decoder, and
resets the ÷ 6 circuit.
Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.
Encoder An active low output designed to drive the zero or negative sense of a
bipolar line driver.
Encoder A low on this pin forces pin 15 and 17 high, the inactive states.
Encoder An active low output designed to drive the one or positive sense of a bipolar
line driver.
5-143









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HD4-15530-8 Даташит, Описание, Даташиты
HD-15530
Pin Description (Continued)
PIN
NUMBER
18
TYPE
NAME
I SERIAL DATA IN
19 I ENCODER ENABLE
20 I SYNC SELECT
21 O SEND DATA
22 I SEND CLOCK IN
23 I ENCODER CLOCK
24 I VCC
I = Input O = Output
SECTION
DESCRIPTION
Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
Encoder A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
Encoder Actuates a Command sync for an input high and Data sync for an input low.
Encoder An active high output which enables the external source of serial data.
Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6
output.
Encoder Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
Both
VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC
(pin 24) to GROUND (pin 12) is recommended.
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK 1 .
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word 2 . When the Encoder is ready to accept data,
the SEND DATA output will go high and remain high for six-
teen ENCODER SHIFT CLOCK periods 3 . During these
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
ENCODER SHIFT CLOCK so it can be sampled on the low-
to-high transition 3 - 4 . After the sync and Manchester II
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word 5 . If ENCODER
ENABLE is held high continuously, consecutive words will be
encoded without an interframe gap. ENCODER ENABLE
must go low by time 5 as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
TIMING
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
0 1 23 4 5 6 7
15 16 17 18 19
VALID
DON’T CARE
DON’T CARE
15 14 13 12 11 10 3 2 1 0
1ST HALF 2ND HALF 15 14 13 12 11
3 210
SYNC SYNC 15 14 13 12 11
3 210
P
P
12
3
FIGURE 1.
45
5-144










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Номер в каталогеОписаниеПроизводители
HD4-15530-8CMOS Manchester Encoder-DecoderIntersil Corporation
Intersil Corporation
HD4-15530-9CMOS Manchester Encoder-DecoderIntersil Corporation
Intersil Corporation

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