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PDF CEF02N6 Data sheet ( Hoja de datos )

Número de pieza CEF02N6
Descripción N-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricantes CET 
Logotipo CET Logotipo



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No Preview Available ! CEF02N6 Hoja de datos, Descripción, Manual

CEF02N6
Sep. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
600V , 1.5A , RDS(ON)=5@VGS=10V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220F full-pak for through hole
G
D
6
G
D
S
TO-220F
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous
-Pulsed
ID
IDM
Drain-Source Diode Forward Current
IS
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperautre Range
PD
TJ,T STG
Limit
600
Ć30
1.5
4.5
4.5
29
0.23
-65 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
RįJC
Thermal Resistance, Junction-to-Ambient
RįJA
6-117
4.3
65
C/W
C/W
http://www.Datasheet4U.com

1 page




CEF02N6 pdf
15
VDS=480V
12 ID=2A
9
6
3
0
0 6 12 18 24
Qg, Total Gate Charge (nC)
Figure 9. Gate Charge
VDD
RL
VIN
D VOUT
VGS
RGEN G
S
Figure 11. Switching Test Circuit
0.2
2
1
D=0.5
CEF02N6
10
1 RDS(ON) Limit
1ms
100m1s0ms
0.1
Tc=25 C
Tj=150C
Single Pulse
0.01
1 10
100 500 1000
VDS, Drain-Source Voltage (V)
Figure 10. Maximum Safe
Operating Area
6
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 12. Switching Waveforms
0.1
0.1
0.05
0.02
0.01
0.01
0.01
0.1
Single Pulse
1 10 100
Square Wave Pulse Duration (msec)
PDM
t1
t2
1. RįJC (t)=r (t) * RįJC
2. RįJC=See Datasheet
3. TJM-TC =P *R įJC (t)
4. Duty Cycle, D=t1/t2
1000
10000
Figure 13. Normalized Thermal Transient Impedance Curve
6-121

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