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PDF HD404818TF Data sheet ( Hoja de datos )
| Número de pieza | HD404818TF | |
| Descripción | 16-digit LCD driver | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD404818TF (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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HD404818 Series
4-Bit Single-Chip Microcomputer
Preliminary
Rev. 2.0
Sept. 1998
Description
The H D4 04 81 8 Seri es of 4-bit single-chip HMCS400 series microcomputers provide high program
productivity. It incorporates a large size memory, LCD controller/driver, voltage comparator, and 32-kHz
watch oscillator circuit.
The HD404818 Series has both standard voltage versions and low voltage versions available. The standard
voltage versions operate at 4.0 V to 6.0 V (mask ROM version) and 4.0 V to 5.5 V (PROM version), while
the low voltage versions operate at 2.7 V to 6.0 V (mask ROM) and 3.0 V to 5.5 V (PROM). Low voltage
versions include an L in their product name.
Standard voltage versions: HD404812, HD404814, HD404816, HD404818, HD4074818
Low voltage versions: HD40L4812, HD40L4814, HD40L4816, HD40L4818, HD407L4818
The HD4074818 and HD407L4818, containing PROMs, are ZTAT™ microcomputers which can
dramatically shorten system development time and smoothly proceed from debugging to mass production.
ZTATTM : Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
w • 2048-word × 10-bit ROM (HD404812, HD40L4812)
w • 4096-word × 10-bit ROM (HD404814, HD40L4814)
w • 6144-word × 10-bit ROM (HD404816, HD40L4816)
. • 8192-word × 10-bit ROM (HD404818, HD40L4818, HD4074818, HD407L4818)
D • 1184-digit × 4-bit RAM
a• 30 I/O pins, including 10 high-current output pins, all CMOS and programmable as I/O pull-up MOS
ta• LCD controller/driver (32 segments × 4 commons)
S• Three timer/counters
h• Clock-synchronous 8-bit serial interface
e• Six interrupt sources
e Two by external sources
t4U.com Four by internal sources
1 page  
HD404818 Series
Pin Description
Pin Number
Pin Number
FP-80B
FP-80A, TFP-80 Pin Name I/O FP-80B
FP-80A, TFP-80 Pin Name I/O
1 79
2 80
31
42
53
64
75
86
97
10 8
11 9
12 10
13 11
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11/VCref
D12/COMP0
D13/COMP1
TEST
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I 39
I 40
I 41
I 42
I 43
29
30
31
32
33
34
35
36
37
38
39
40
41
R32/INT0
R33/INT1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
14 12
X1
I 44
42
SEG12 O
15 13
X2
O 45
43
SEG13 O
16 14
GND
46 44
SEG14 O
17 15
18 16
19 17
20 18
21 19
22 20
23 21
24 22
25 23
26 24
27 25
28 26
29 27
30 28
R00/SCK
R01/SI
R02/SO
R03
R10
R11
R12
R13
R20
R21
R22
R23
R30
R31/TIMO
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
45
46
47
48
49
50
51
52
53
54
55
56
57
58
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
O
O
O
O
O
O
O
O
O
O
O
O
O
O
5
5 Page 
HD404818 Series
RAM Memory Map
The MCU also contains a 1,184-digit × 4-bit RAM as the data and stack area. In addition to these areas,
interrupt control bits and special function registers are mapped on the RAM memory space. The RAM
memory map (figure 2) is described in the following paragraphs.
Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt
control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag
cannot be set by software. The RSP bit is used only to reset the stack pointer.
Special Function Registers Area ($004 to $01F, $024 to $03F): The special function registers are the
mode or data registers for the serial interface, timer/counters, LCD, and the data control registers for the
I/O ports. These registers are classified into three types: write-only, read-only, and read/write as shown in
figure 2.
The SEM/REM and SEMD/REMD instructions are available for the LCD control register (LCR).
Other registers cannot be accessed by RAM bit manipulation instructions.
Register Flag Area ($020 to $023): Consist of the LSON, WDON, TGSP, and DTON flags which are bit
registers accessible by the RAM bit manip ula tion instruction.
The WDON flag can only be set, and only by the SEM/SEMD instruction.
The DTON flag can be set, reset, and tested by the SEM/SEMD, REM/REMD, and TMD instructions. Note
that the DTON flag is active only in subactive mode, and is normally reset in active mode.
LCD Data Area ($050 to $06F): Locations $050 to $06F store the LCD data which is automatically
transmitted to the segment driver as display data. The LCD is illuminated with 1s and faded with 0s. This
area can be used as a data area.
Data Area ($040 to $2CF, $100 to $2CF; Bank 0/1): The 16 digits of $040 through $04F are called
memory registers (MR) and are accessible by the LAMR and XMRA instructions (figure 4). 464 digits of
$100 through $2CF are selected as bank 0 or 1 depending on the value of the V register.
Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL or
CALL instruction) and interrupts are processed. This area can be used as a 16-level nesting stack in which
one level requires 4 digits.
Figure 4 shows the save condition. The program counter is restored by the RTN and RTNI instructions. The
status and carry flags are restored only by the RTNI instruction. This area, when not used as a stack, is
available as a data area.
11
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