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PDF HD49323AF Data sheet ( Hoja de datos )
| Número de pieza | HD49323AF | |
| Descripción | CDS/AGC & 10-bit A/D Converter | |
| Fabricantes | Hitachi Semiconductor | |
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HD49323AF-01
CDS/AGC & 10-bit A/D Converter
ADE-207-262A (Z)
2nd Edition
Apr. 1999
Description
The HD49323AF-01 is a CMOS IC that provides CCD-AGC analog processing (CDS/AGC) suitable for
CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
Functions
• Correlated Double Sampling
• AGC
• Sample hold
• Offset compensation
• Serial interface control
• 10-bit ADC
• 3 V single operation (2.7 V to 3.6 V)
• Power dissipation: 198 mW (Typ)
• Maximum frequency: 20 MHz (Min)
Features
• Good suppression of CCD output low-frequency noise is achieved through the use of S/H type
correlated double sampling.
• A high S/N ratio is achieved through the use of a AGC type amplifier, and high sensitivity is provided
by a wide cover range.
• An auto offset circuit provides compensation of output DC offset voltage fluctuations due to variations
in AGC amplifier gain.
• AGC, standby mode, offset control, etc., is possible via a serial interface.
• High precision is provided by a 10-bit-resolution A/D converter.
• Version of Hitachi’s previous-generation HD49322BF with improved functions and performance,
including in particular an approximately 3.0 dB improvement in S/N.
1 page  
Input/Output Equivalent Circuit
Pin Name
Digital output
D0 to D9
Equivalent Circuit
DIN
Digital input
Analog input
ADCLK
OBP
SPBLK
SPSIG
CS
SCK
SDATA
PBLK
OE
CDSIN
STBY
or
OE
Digital
input
*1
70kΩ
(Typ)
CDSIN
HD49323AF-01
DVDD
Digital
output
Connected to
VRM internally
Reference voltage input
VRT
VRM
VRB
VRM2
VRT VRM VRM2 VRB
++
−−
Clamp
CLP
AVDD
CLP
Connected to
VRM internally
Internal bias
BIAS
Note: 1. Applies to OE and PBLK.
AVDD
BIAS
5
5 Page 
Timing Chart
Figure 3 shows the output timing.
HD49323AF-01
• Sampling timing chart
0123456
CDSIN N N+1 N+2 N+3 N+4 N+5 N+6
SPBLK
SPSIG
ADCLK
D0 to D9
N−5
N−4
N−3
N−2
N−1
N
Figure 3 Output Timing
• The ADC output signals (D0 to D9) are output at the rising edge of ADCLK.
• The pipeline delay is 5 clocks.
• Regarding OBP
H period
OBP > 12fs
Note: The phase of OBP is for a low setting of the serial data OBP INV bit.
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet HD49323AF.PDF ] | |
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