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PDF HD64570F8I Data sheet ( Hoja de datos )
| Número de pieza | HD64570F8I | |
| Descripción | Serial Communications Adaptor | |
| Fabricantes | Hitachi Semiconductor | |
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HD64570 SCA
Serial Communications Adaptor
User’s Manual
ADE-602-035B
Rev. 3.0
August 28, 1998
Hitachi Company or Division
1 page  
Preface
The HD64570 serial communications adaptor (SCA) peripheral chip enables a host
microprocessor to perform asynchronous, byte-synchronous, or bit-synchronous serial
communication. Its two full-duplex, multiprotocol serial channels support a wide variety of
protocols, including frame relay, LAPB, LAPD, bisync, and ™DDCMP. Its built-in direct
memory access controller (DMAC) is equipped with a 32-stage FIFO and can execute chained-
block transfers. Due to its DMAC and 16-bit bus interface, the SCA supports serial data transfer
rates up to 12 Mbits/s without monopolizing the bus, even in full-duplex communication. Other
on-chip features of the SCA, including four types of MPU interfaces, a bus arbiter, timers, and an
interrupt controller, provide added functionality in a wide range of applications, such as frame
relay exchanges/system multiplexes, private branch exchanges, computer networks, workstations,
ISDN terminals, and facsimile.
™DDCMP is a trademark of Digital Equipment Corporation.
Rev. 0, 07/98, page i of 11
5 Page 
Contents
Section 1 Overview ...........................................................................................................
1.1 Overview............................................................................................................................
1.2 Features..............................................................................................................................
1.3 Basic Functions..................................................................................................................
1.4 Block Diagram...................................................................................................................
1.5 Protocol Support................................................................................................................
1.5.1 Asynchronous Mode ............................................................................................
1.5.2 Byte-Synchronous Mode......................................................................................
1.5.3 Bit-Synchronous Mode ........................................................................................
1.6 Built-In Registers...............................................................................................................
1.6.1 Low-Power Mode Control Registers....................................................................
1.6.2 Interrupt Control Registers ...................................................................................
1.6.3 MSCI Registers ....................................................................................................
1.6.4 DMAC Registers common to channels 0 to 3......................................................
1.6.5 DMA Registers provided separately for channels 0 to 3......................................
1.6.6 Timer Registers ....................................................................................................
1.6.7 Wait Controller Registers .....................................................................................
1.7 General Description of Functions......................................................................................
1.7.1 Operating Modes of Serial Section ......................................................................
1.7.2 Transmission Formats ..........................................................................................
1.7.3 Transmission Error Detection ..............................................................................
1.7.4 Transmission Codes..............................................................................................
1.7.5 Transmit/Receive Clock Selection .......................................................................
1.7.6 Maximum Bit Rates..............................................................................................
1.7.7 Transmitter ...........................................................................................................
1.7.8 Receiver................................................................................................................
1.7.9 DMAC..................................................................................................................
1.7.10 DMA Buffer Chaining..........................................................................................
1.7.11 Descriptor Structure..............................................................................................
1.7.12 Bus Arbiter ...........................................................................................................
1.7.13 Interrupt Control...................................................................................................
1.7.14 Timers...................................................................................................................
1.7.15 Wait Controller.....................................................................................................
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Section 2 Pin Arrangements and Functions ............................................................... 41
2.1 Pin Arrangements .............................................................................................................. 41
2.2 Pin Functions ..................................................................................................................... 43
Rev. 0, 07/98, page i of 11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HD64570F8I.PDF ] | |
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