HD6475328F PDF даташит
Спецификация HD6475328F изготовлена «Hitachi Semiconductor» и имеет функцию, называемую «Manual Gives a Hardware Description». |
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Детали детали
Номер произв | HD6475328F |
Описание | Manual Gives a Hardware Description |
Производители | Hitachi Semiconductor |
логотип |
30 Pages
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H8/532 Hardware Manual
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Preface
The H8/532 is a high-performance single-chip Hitachi-original microcomputer, featuring a high-
speed CPU with 16-bit internal data paths and a full complement of on-chip supporting modules.
The H8/532 is an ideal microcontroller for a wide variety of medium-scale devices, including both
office and industrial equipment and consumer products.
Its highly orthogonal instruction set is designed for fast execution of programs coded in the high-
level C language.
On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D
converter, I/O ports, and other functions for compact implementation of high-performance
application systems.
The H8/532 is available in both a ZTAT™ version* with on-chip PROM, ideal for the early stages
of production or for products with frequently-changing specifications, and a masked-ROM version
suitable for volume production.
This manual gives a hardware description of the H8/532. For details of the instruction set, refer to
the H8/500 Series Programming Manual, which applies to all chips in the H8/500 Series.
* ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd.
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Contents
Section 1 Overview
1.1 Features ··································································································································1
1.2 Block Diagram ·······················································································································4
1.3 Pin Arrangements and Functions ···························································································5
1.3.1 Pin Arrangement ·········································································································5
1.3.2 Pin Functions ··············································································································8
Section 2 MCU Operating Modes and Address Space
2.1 Overview ······························································································································23
2.2 Mode Descriptions ···············································································································24
2.3 Address Space Map ··············································································································25
2.3.1 Page Segmentation ····································································································25
2.3.2 Page 0 Address Allocations ······················································································27
2.4 Mode Control Register (MDCR) ·························································································29
Section 3 CPU
3.1 Overview ······························································································································31
3.1.1 Features ·····················································································································31
3.1.2 Address Space ···········································································································32
3.1.3 Register Configuration ······························································································33
3.2 CPU Register Descriptions ··································································································34
3.2.1 General Registers ······································································································34
3.2.2 Control Registers ······································································································35
3.2.3 Initial Register Values ·······························································································40
3.3 Data Formats ························································································································41
3.3.1 Data Formats in General Registers ···········································································41
3.3.2 Data Formats in Memory ··························································································42
3.4 Instructions ···························································································································44
3.4.1 Basic Instruction Formats ·························································································44
3.4.2 Addressing Modes ····································································································45
3.4.3 Effective Address Calculation ···················································································47
3.5 Instruction Set ······················································································································50
3.5.1 Overview ···················································································································50
3.5.2 Data Transfer Instructions ·························································································52
3.5.3 Arithmetic Instructions ·····························································································53
3.5.4 Logic Operations ·······································································································54
3.5.5 Shift Operations ········································································································55
3.5.6 Bit Manipulations ······································································································56
3.5.7 Branching Instructions ······························································································57
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