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PDF HD74AC107 Data sheet ( Hoja de datos )
| Número de pieza | HD74AC107 | |
| Descripción | Dual JK Flip-Flop (with Separate Clear and Clock) | |
| Fabricantes | Hitachi Semiconductor | |
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HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;
4) transfer information from master to slave.
Features
• Outputs Source/Sink 24 mA
• HD74ACT107 has TTL-Compatible Inputs
Pin Arrangement
J1 1
Q1 2
Q1 3
K1 4
Q2 5
Q2 6
GND 7
(Top view)
14 VCC
13 CD1
12 CP1
11 K2
10 CD2
9 CP2
8 J2
1 page  
HD74AC107/HD74ACT107
AC Characteristics: HD74ACT107
Item
Maximum clock
frequency
Symbol VCC (V)*1
fmax 5.0
Ta = +25°C
CL = 50 pF
Min Typ
100 —
Propagation delay
CP to Q or Q
t PLH
5.0
Propagation delay
CP to Q or Q
t PHL
5.0
Propagation delay
CD to Q
t PLH
5.0
Propagation delay
CD to Q
t PHL
5.0
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
1.0
1.0
1.0
1.0
9.5
10.5
8.5
8.5
Max
—
12.5
13.0
11.0
11.0
Ta = –40°C to +85°C
CL = 50 pF
Min Max
80 —
Unit
MHz
1.0 13.5 ns
1.0 14.0
1.0 12.0
1.0 12.0
Operating Requirements: HD74ACT107
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1 Typ
Setup time
J or k to CP
tsu 5.0 2.5
Hold time
CP to J or k
th 5.0 0.0
Pulse width
CP or CD
tw 5.0 4.5
Recovery time
CD to CP
trec 5.0 —
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C
to +85°C
CL = 50 pF
Guaranteed Minimum
7.0 8.0
1.5 1.5
7.0 8.0
3.0 3.0
Unit
ns
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
CIN
CPD
Typ
4.5
35.0
Unit
pF
pF
Condition
VCC = 5.5 V
VCC = 5.0 V
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HD74AC107.PDF ] | |
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