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PDF HD74AC112 Data sheet ( Hoja de datos )

Número de pieza HD74AC112
Descripción Dual JK Negative Edge-Triggered Flip-Flop
Fabricantes Hitachi Semiconductor 
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No Preview Available ! HD74AC112 Hoja de datos, Descripción, Manual

HD74AC112/HD74ACT112
Dual JK Negative Edge-Triggered Flip-Flop
Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to
each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level
of the J and K inputs may change when the clock is High and the bistable will perform according to the
Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs
on the falling edge of the clock pulse.
Features
Outputs Source/Sink 24 mA
HD74ACT112 has TTL-Compatible Inputs
Pin Arrangement
CP1 1
K1 2
J1 3
SD1 4
Q1 5
Q1 6
Q2 7
GND 8
(Top view)
16 VCC
15 CD1
14 CD2
13 CP2
12 K2
11 J2
10 SD2
9 Q2

1 page




HD74AC112 pdf
HD74AC112/HD74ACT112
AC Characteristics: HD74ACT112
Item
Maximum clock
frequency
Symbol VCC (V)*1
fmax 5.0
Ta = +25°C
CL = 50 pF
Min Typ
100 —
Propagation delay
CP to Q or Q
t PLH
5.0
Propagation delay
CP to Q or Q
t PHL
5.0
Propagation delay
CD, SD to Q or Q
t PLH
5.0
Propagation delay
CD, SD to Q or Q
t PHL
5.0
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
1.0
1.0
1.0
1.0
10.5
10.5
8.0
10.5
Max
13.0
13.0
10.0
12.5
Ta = –40°C to +85°C
CL = 50 pF
Min Max
80 —
Unit
MHz
1.0 14.0 ns
1.0 14.0
1.0 11.0
1.0 13.5
AC Operating Requirements: HD74ACT112
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1 Typ
Setup time
J or K to CP
tsu 5.0 2.5
Hold time
CP to J or K
th 5.0 0.0
Pulse width
CP or CD or SD
tw 5.0 4.5
Recovery time
CD , SD to CP
trec 5.0 –2.5
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C
to +85°C
CL = 50 pF
Guaranteed Minimum
7.0 8.0
1.5 1.5
7.0 8.0
3.0 3.0
Unit
ns
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
CIN
CPD
Typ
4.5
35.0
Unit
pF
pF
Condition
VCC = 5.5 V
VCC = 5.0 V
5

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