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HD74AC174 PDF даташит

Спецификация HD74AC174 изготовлена ​​​​«Hitachi Semiconductor» и имеет функцию, называемую «Hex D-Type Flip-Flop with Master Reset».

Детали детали

Номер произв HD74AC174
Описание Hex D-Type Flip-Flop with Master Reset
Производители Hitachi Semiconductor
логотип Hitachi Semiconductor логотип 

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HD74AC174 Даташит, Описание, Даташиты
HD74AC174
Hex D-Type Flip-Flop with Master Reset
Description
The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered
storage register. The information on the D inputs is transferred to storage during the Low-to-High clock
transition. The device has a Master Reset to simultaneously clear all flip-flops.
Feature
Outputs Source/Sink 24 mA
Pin Arrangement
MR 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
(Top view)
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP









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HD74AC174 Даташит, Описание, Даташиты
HD74AC174
Logic Symbol
D0 D1 D2 D3 D4 D5
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5
Pin Names
D0 to D5
CP
MR
Q0 to Q5
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Functional Description
The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The
Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the
corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the
Master Reset (MR) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is
useful for applications where the true output only is required and the Clock and Master Reset are common
to all storage elements.
Truth Table
Inputs
MR
CP
LX
H
H
HL
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
: Low-to-High Transition of Clock
D
X
H
L
X
Output
Q
L
H
L
Q
2









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HD74AC174 Даташит, Описание, Даташиты
Logic Diagram
HD74AC174
MR CP D5 D4 D3 D2 D1 D0
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
Q5 Q4 Q3 Q2 Q1 Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
Item
Maximum quiescent supply current
Symbol Max
ICC 80
Unit
µA
Maximum quiescent supply current ICC 8.0 µA
Condition
VIN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
VIN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
AC Characteristics: HD74AC174
Item
Maximum clock
frequency
Symbol
f max
VCC (V)*1
3.3
5.0
Ta = +25°C
CL = 50 pF
Min Typ
90 100
100 125
Propagation delay
t PLH
3.3
CP to Qn
5.0
Propagation delay
t PHL
3.3
CP to Qn
5.0
Propagation delay
t PHL
3.3
MR to Qn
5.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
1.0
1.0
1.0
1.0
1.0
1.0
9.0
6.0
8.5
6.0
9.0
7.0
Max
11.5
8.5
11.0
8.0
11.5
9.0
Ta = –40°C to +85°C
CL = 50 pF
Min Max
70 —
100 —
1.0 12.5
1.0 9.5
1.0 12.0
1.0 9.0
1.0 12.5
1.0 10.5
Unit
MHz
ns
ns
ns
3










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