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8N4QV01 PDF даташит

Спецификация 8N4QV01 изготовлена ​​​​«Integrated Device Technology» и имеет функцию, называемую «IDT8N4QV01».

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Номер произв 8N4QV01
Описание IDT8N4QV01
Производители Integrated Device Technology
логотип Integrated Device Technology логотип 

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8N4QV01 Даташит, Описание, Даташиты
Quad-Frequency Programmable
VCXO
IDT8N4QV01 REV G
DATA SHEET
General Description
The IDT8N4QV01 is a Quad-Frequency Programmable VCXO with
very flexible frequency and pull-range programming capabilities.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead ceramic 5mm x
7mm x 1.55mm package.
Besides the 4 default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4QV01 can be programmed via the I2C
interface to any output clock frequency between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL, P, M and N divider registers (P, MINT, MFRAC
and N), reprogramming those registers to other frequencies under
control of FSEL0 and FSEL1 is supported. The extended
temperature range supports wireless infrastructure, tele-
communication and networking end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I2C
I2C programming interface for the output clock frequency, APR
and internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
Absolute pull-range (APR) programmable from ±4.5ppm to
±754.5ppm
One 2.5V or 3.3V LVDS differential clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.494ps
(typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.594ps
(typical)
2.5V or 3.3V supply voltage modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC ÷P
114.285 MHz
VC
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
A/D
2
7
Pullup
Pullup
Pullup
PFD FemtoClock® NG
&
VCO
÷N
LPF 1950-2600MHz
÷MINT, MFRAC
25
Configuration Register (ROM)
(Frequency, APR, Polarity)
7
I2C Control
Pin Assignment
Q
nQ
VC 1
8 VDD
OE 2
7 nQ
GND 3
6Q
IDT8N4QV01 REV G DATA SHEET
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N4QV01GCD MARCH 6, 2012 1 ©2012 Integrated Device Technology, Inc.









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8N4QV01 Даташит, Описание, Даташиты
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 1. Pin Descriptions
Number
Name
1 VC
2 OE
3 GND
4, 5 FSEL0, FSEL1
6, 7 Q, nQ
8 VDD
9 SDATA
10 SCLK
Type
Input
Input
Power
Pullup
Input Pulldown
Output
Power
Input
Input
Pullup
Pullup
Description
VCXO Control Voltage. The control voltage versus frequency characteristics are
set by the ADC_GAIN[5:0] register bits. (see Table 3C).
Output enable pin. See Table 3B for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Default frequency select pins. See Table 3A for function and Table 8 for the
default frequency order codes. LVCMOS/LVTTL interface levels.
Differential clock output. LVDS interface levels.
Power supply pin.
I2C Data Input. LVCMOS/LVTTL interface levels.
I2C Clock Input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
Test Conditions
FSEL[1:0], SDATA, SCLK
VC
Minimum
Typical
5.5
10
50
50
Maximum
Units
pF
pF
k
k
IDT8N4QV01GCD MARCH 6, 2012 2 ©2012 Integrated Device Technology, Inc.









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8N4QV01 Даташит, Описание, Даташиты
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Function Tables
Table 3A. Default Frequency Selection
Input
FSEL1
FSEL0
Operation
0 (default)
0 (default)
Default frequency 0
0 1 Default frequency 1
1 0 Default frequency 2
1 1 Default frequency 3
NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See
programming section for details.
Table 3B. OE Configuration
Input
OE Output Enable
0 Outputs Q, nQ are in high-impedance state.
1 (default)
Outputs are enabled.
NOTE: OE is an asynchronous control.
IDT8N4QV01GCD MARCH 6, 2012 3 ©2012 Integrated Device Technology, Inc.










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Номер в каталогеОписаниеПроизводители
8N4QV01IDT8N4QV01Integrated Device Technology
Integrated Device Technology

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