HD74ALVCH162500 PDF даташит
Спецификация HD74ALVCH162500 изготовлена «Hitachi Semiconductor» и имеет функцию, называемую «18-bit Universal Bus Transceivers with 3-state Outputs». |
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Детали детали
Номер произв | HD74ALVCH162500 |
Описание | 18-bit Universal Bus Transceivers with 3-state Outputs |
Производители | Hitachi Semiconductor |
логотип |
13 Pages
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HD74ALVCH162500
18-bit Universal Bus Transceivers with 3-state Outputs
ADE-205-181 (Z)
Preliminary
1st. Edition
December 1996
Description
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB
and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the high to
low transition of CLKAB. Output enable OEAB is active high. When OEAB is high, the B port
outputs are active. When OEAB is low, the B port outputs are in the high impedance state. Data flow
for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high, and OEBA is active low). Active bus hold circuitry is provided
to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up
to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
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HD74ALVCH162500
Function Table *3
Inputs
Output B
OEAB
LEAB
CLKAB
A
L XXXZ
HHXL L
HHXHH
HL ↓ L L
HL ↓ HH
H L H X B0 *1
H L L X B0 *2
H : High level
L : Low level
X : Immaterial
Z : High impedance
↓ : High to low transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. Output level before the indicated steady state input conditions were established, provided
that CLKAB was low before LEAB went low.
3. A to B data flow is show; B to A flow is similar but uses OEBA, LEBA, and CLKBA.
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Pin Arrangement
HD74ALVCH162500
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
VCC 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
VCC 22
A16 23
A17 24
GND 25
A18 26
OEBA 27
LEBA 28
(Top view)
56 GND
55 CLKAB
54 B1
53 GND
52 B2
51 B3
50 VCC
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 VCC
34 B16
33 B17
32 GND
31 B18
30 CLKBA
29 GND
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Номер в каталоге | Описание | Производители |
HD74ALVCH162500 | 18-bit Universal Bus Transceivers with 3-state Outputs | Hitachi Semiconductor |
HD74ALVCH162501 | 18-bit Universal Bus Transceivers with 3-state Outputs | Hitachi Semiconductor |
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