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HD74ALVCH16260 PDF даташит

Спецификация HD74ALVCH16260 изготовлена ​​​​«Hitachi Semiconductor» и имеет функцию, называемую «12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs».

Детали детали

Номер произв HD74ALVCH16260
Описание 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
Производители Hitachi Semiconductor
логотип Hitachi Semiconductor логотип 

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HD74ALVCH16260 Даташит, Описание, Даташиты
HD74ALVCH16260
12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
ADE-205-135B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two
separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical
applications include multiplexing and / or demultiplexing of address and data information in
microprocessor or bus interface applications. This device is also useful in memory interleaving
applications. Three 12-bit I / O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and /
or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and / or data
information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is
transparent. When the latch enable input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high. Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
Features
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors









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HD74ALVCH16260 Даташит, Описание, Даташиты
HD74ALVCH16260
Function Table
Inputs
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
SEL
H
H
H
L
L
L
X
LE1B
LE2B
HX
HX
LX
XH
XH
XL
XX
B-to-A (OEB = H)
OEA
L
L
L
L
L
L
H
Output A
H
L
A0 *1
H
L
A0 *1
Z
Inputs
A
H
L
H
L
H
L
X
X
X
X
X
LEA1B
H
H
H
H
L
L
L
X
X
X
X
LEA2B
H
H
L
L
H
H
L
X
X
X
X
OE1B
OE2B
LL
LL
LL
LL
LL
LL
LL
HH
LH
HL
LL
A-to-B (OEA = H)
Outputs
1B
H
L
H
L
1B0 *1
1B0 *1
1B0 *1
Z
Active
Z
Active
2B
H
L
2B0 *1
2B0 *1
H
L
2B0 *1
Z
Z
Active
Active
H : High level
L : Low level
X : Immaterial
Z : High impedance
Note: 1. Output level before the indicated steady state input conditions were established.
2









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HD74ALVCH16260 Даташит, Описание, Даташиты
Pin Arrangement
HD74ALVCH16260
OEA 1
LE1B 2
2B3 3
GND 4
2B2 5
2B1 6
VCC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
VCC 22
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
(Top view)
56 OE2B
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
50 VCC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 VCC
34 1B6
33 1B5
32 GND
31 1B4
30 LEA1B
29 OE1B
3










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