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HD74ALVCH16270 PDF даташит

Спецификация HD74ALVCH16270 изготовлена ​​​​«Hitachi Semiconductor» и имеет функцию, называемую «12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs».

Детали детали

Номер произв HD74ALVCH16270
Описание 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
Производители Hitachi Semiconductor
логотип Hitachi Semiconductor логотип 

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HD74ALVCH16270 Даташит, Описание, Даташиты
HD74ALVCH16270
12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
ADE-205-137 (Z)
Preliminary 1st. Edition
May 1996
Description
The HD74ALVCH16270 is used in applications where data must be transferred from a narrow high
speed bus to a wide lower frequency bus. The device provides synchronous data exchange between the
two ports. Data is stored in the internal registers on the low to high transition of the clock (CLK) input
when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A
outputs. For data transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path,
with a single storage register in the A to 2B path. Proper control of the CLKENA inputs allows two
sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is
controlled by the active low output enables (OEA, OEB). The control terminals are registered to
synchronize the bus direction changes with CLK. Active bus hold circuitry is provided to hold unused
or floating data inputs at a valid logic level.
Features
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors









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HD74ALVCH16270 Даташит, Описание, Даташиты
HD74ALVCH16270
Function Table
Inputs
CLK
OEA
H
H
L
L
OEB
H
L
H
L
Outputs
A
Z
Z
Active
Active
Output enable
1B, 2B
Z
Active
Z
Active
Inputs
CLKENA1
L
L
L
L
H
H
H
CLKENA2
H
H
L
L
L
L
H
CLK
X
Outputs
A 1B
L L *2
H H *2
L L *2
H H *2
L 1B0 *1
H 1B0 *1
X 1B0 *1
A-to-B storage (OEB = L)
2B
2B0 *1
2B0 *1
L
H
L
H
2B0 *1
Inputs
CLKEN1B
H
X
L
L
X
X
CLKEN2B
X
H
X
X
L
L
CLK
X
X
SEL 1B
HX
LX
HL
HH
LX
LX
B-to-A storage (OEA = L)
2B
X
X
X
X
L
H
Output A
A0 *1
A0 *1
L
H
L
H
H : High level
L : Low level
X : Immaterial
Z : High impedance
: Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. Two CLK edges are needed to propagate data.









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HD74ALVCH16270 Даташит, Описание, Даташиты
Pin Arrangement
HD74ALVCH16270
OEA 1
CLKEN1B 2
2B3 3
GND 4
2B2 5
2B1 6
VCC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
VCC 22
1B1 23
1B2 24
GND 25
1B3 26
CLKEN2B 27
SEL 28
(Top view)
56 OEB
55 CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 VCC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 VCC
34 1B6
33 1B5
32 GND
31 1B4
30 CLKENA1
29 CLK










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