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PDF HD74ALVCH162820 Data sheet ( Hoja de datos )

Número de pieza HD74ALVCH162820
Descripción 3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs
Fabricantes Hitachi Semiconductor 
Logotipo Hitachi Semiconductor Logotipo



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HD74ALVCH162820
3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs
ADE-205-185B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH162820 flip flops are edge triggered D-type flip flops. On the positive transition of the
clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can
be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high
impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.
The high impedance state and increased drive provide the capability to drive bus line without need for
interface or pullup components. OE does not affect the internal operations of the flip flops. Old data can
be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold
circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are
designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot.
Features
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±12 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26 series resistors, so no external resistors are required.

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HD74ALVCH162820 pdf
Logic Diagram
1OE 1
2OE 28
CLK 56
D1 55
C1
1D
HD74ALVCH162820
2
1Q1
3
1Q2
To nine other channels
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HD74ALVCH162820 arduino
Package Dimensions
14.00
+0.3
–0.1
56
29
1
0.20
+0.1
–0.05
0.50
0.08 M
28
0.40 Max
0.10
HD74ALVCH162820
Unit : mm
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
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