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PDF HD74BC563A Data sheet ( Hoja de datos )

Número de pieza HD74BC563A
Descripción Octal D Type Transparent Latches With 3 State Outputs
Fabricantes Hitachi Semiconductor 
Logotipo Hitachi Semiconductor Logotipo



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HD74BC563A
Octal D Type Transparent Latches With 3 State Outputs
ADE-205-040 (Z)
Rev. 0
June 1993
Description
HD74BC563A provides high drivability and operation equal to or better than high speed bipolar standard
logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high
speed bipolar logic IC, when the frequency is 10 MHz. The device has eight D type latches with three state
outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs.
When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable
returns high again. When a high logic level is applied to the output control input, all outputs go to a high
impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
Input/Output are at high impedance state when power supply is off.
Built in input pull up circuit can make input pins be open, when not used.
TTL level input
Wide operating temperature range
Ta = –40 to +85°C.
Function Table
Output Control
Latch Enable
Data
Output Q
LH H L
LH
L
H
L L X Q0
HX X Z
H : High level
L : Low level
X : Immaterial
Z : High impedance
Q0 : Level of Q before the indicated steady state input conditions were established.

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HD74BC563A pdf
Switching Test Method (CL = 50 pF)
Item
Propagation
delay time
DQ
LE Q
Output enable time
Output disable time
Setup time
Hold time
Pulse width
Input capacitance
Output capacitance
Symbol
t PLH
t PHL
t PLH
t PHL
t ZH
t ZL
t HZ
t LZ
tS(H)
tS(L)
th(H)
th(L)
tw
CIN
CO
Ta = 25°C
VCC = 5.0 V
Min Max
3.0 8.0
3.0 8.0
3.0 8.0
3.0 8.0
3.0 9.0
3.0 9.0
3.0 8.0
3.0 8.0
2.0 —
2.0 —
2.0 —
2.0 —
6.0 —
3.0(Typ)
15.0(Typ)
HD74BC563A
Ta = –40 to 85°C
VCC = 5.0 V ±10%
Min Max
3.0 10.0
3.0 10.0
3.0 10.0
3.0 10.0
3.0 11.0
3.0 11.0
3.0 10.0
3.0 10.0
2.0 —
2.0 —
2.0 —
2.0 —
6.0 —
Unit Test Conditions
ns See under figure
ns
ns
ns
ns
ns
ns
pF VIN = VCC or GND
pF VO = VCC or GND
Test Circuit
VCC
Input
Pulse Generator
Zout = 50
Input
Pulse Generator
Zout = 50
VCC
OC
Output
1D to 8D
1Q to 8Q
CL=
LE 50 pF
500
450
50 Scope
Notes:
1. CL includes probe and jig capacitance.
2. OPEN: tPLH, tPHL, tZH, tHZ, th, ts, tw
7V: tZL, tLZ
*2
OPEN
7V
5

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